Ultra-fine trench circuit on polymer film

Hondo, Takaharu; Nitta, Yosuke; Nakamura, Kei; Hirano, Hiroyuki; Saruta, Masanobu; Inoue, Toshiaki; Nakao, Osamu

doi:10.1109/ectc.2013.6575563

Cited by 4 publications

(4 citation statements)

References 3 publications

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“…Atotech and Amkor have demonstrated Via 2 processes down to 10 m line features with trench filling processes by excimer laser and copper plating processes [7][8]. Fujikura reported one of the most advanced trench circuit technology to create 2 m line width and 10 m micro-via diameter [9]. However, this demonstration is limited to single layer vias and there was no demonstration of a multilayer wiring structure leading to fine-bump pitch micro-via structures.…”

Section: Introductionmentioning

confidence: 98%

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

Suzuki¹,

Takagi

Tummala

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper describes the first demonstration of 10 m diameter interlayer vias in low-moisture uptake and low surface-roughness dry film polymer dielectric for multilayered re-distribution layer (RDL) structures to achieve 50 m bump pitch in high density organic and glass interposers. A new series of polymer dry films, ZS-100, at 10 m thickness were deposited on thin and low CTE organic or glass cores using double-sided vacuum lamination processes. The ultra-small vias were fabricated by 248nm KrF excimer laser drilling, followed by electroless and electrolytic copper plating. Fully-filled via structures were successfully fabricated without any chemical-mechanical polishing. The processes demonstrated in this paper achieve much finer bump pitch than current organic packages, and can be scaled to large panels leading to lower cost than previous work in fine pitch Si interposers using back-end of line (BEOL) wafer processes.

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Section: Introductionmentioning

confidence: 98%

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

Suzuki¹,

Takagi

Tummala

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…Using additive manufacturing techniques, fabrication of traces down to 25 μm is now possible but with a manufacturing cost of 7–10 k$ . One of the limitations imposed by the traditional wet-etching processes is the isotropic etching rate of etchant solutions for copper which limits the controllability of the aspect ratio (i.e., width/height) of the traces. , For example, traces with an aspect ratio of 1 cannot be easily fabricated with the traditional PCB fabrication. Ion-mill or focused ion beam can be used to etch copper atoms with an excellent spatial resolution, but they are time-consuming, require long exposure of the substrate to a high vacuum environment (leading to degassing of the substrate, and increasing the surface roughness), and are not economically viable .…”

Section: Introductionmentioning

confidence: 99%

A New Approach for Microfabrication of Printed Circuit Boards with Ultrafine Traces

Mirvakili

Broderick

Langer

2019

ACS Appl. Mater. Interfaces

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The advances in micro/nanofabrication techniques have enabled miniaturization of printed circuit boards (PCBs) for various applications such as portable devices, smart sensors, and IoTs, to name a few. PCBs provide electrical connectivity between the components as well as mechanical support. Down-scaling of PCBs is crucial for miniaturization of large systems and devices. Currently, microtraces down to 25 μm can be microfabricated with the current microfabrication processes at an industrial scale. In the present work, we report a new approach for microfabrication of PCBs with trace widths down to 3 μm on commercially available PCB substrates. We used electroplating/electroetching, sputtering, and photolithography to achieve these fine trace sizes. The proposed fabrication technique can be used in microelectronics, system on chip, MEMS, and miniaturized circuits and systems in general.

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“…IC packaging substrate as a special printed circuit board (PCB) for packaging semiconductor chip serves as a multifunctional carrier to protect chips from potential damage and provide rigid support, electrical response and power distribution (Chien et al , 2007; Dong et al , 2006; Dow et al , 2007; Ko et al , 2006). High-density IC packaging substrates are needed to meet the requirement of miniaturization and multifunctionalization for electric products (Hondo et al , 2013). Fine copper electrodeposition plays a significant role in the interconnection of advanced chips and IC substrates, as current electronic products with high performance design call for higher density of interconnection (Kondo et al , 2010; Liu et al , 2010; Tsai and Huang, 2011).…”

Section: Introductionmentioning

confidence: 99%

Improvement of plating uniformity for copper patterns of IC substrate with multi-physics coupling simulation

Xiang

Chen

Wang

et al. 2018

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Purpose Optimized plating conditions, included proper designs of insulating shield (IS), auxiliary cathode (AC) and different patterns, contribute to the uniformity enhancement of copper deposition. Design/methodology/approach Plating experiments were implemented in vertical continuous plating (VCP) line for manufacturing in different conditions. Multiphysics coupling simulation was brought to investigate and predict the plating uniformity improvement of copper pattern. In addition, the numerical model was based on VCP to approach the practical application. Findings With disproportionate current distribution, different plating pattern design formed diverse copper thickness distribution (CTD). IS and AC improved plating uniformity of copper pattern because of current redistribution. Moreover, optimized plating condition for effectively depositing more uniformed plating copper layer in varied pattern designs were derived by simulation and verified by plating experiment. Originality/value The comparison between experiment and simulation revealed that multiphysics coupling is an efficient, reliable and of course environment-friendly tool to perform research on the uniformity of pattern plating in manufacturing.

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Ultra-fine trench circuit on polymer film

Cited by 4 publications

References 3 publications

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

Thin polymer dry-film dielectric material and a process for 10 um interlayer vias in high density organic and glass interposers

A New Approach for Microfabrication of Printed Circuit Boards with Ultrafine Traces

Improvement of plating uniformity for copper patterns of IC substrate with multi-physics coupling simulation

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