Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

Abstract

This paper presents an ultra-high-throughput decoder architecture for NB-LDPC codes based on the Hybrid Extended Min-Sum algorithm. We introduce a new processing block that updates a check node and its associated variable nodes in a fully pipelined way, thus allowing the decoder to process one row of the parity check matrix per clock cycle. The work specifically focuses on a rate 5/6 code of size (N, K) = (144, 120) symbols over GF(64). The synthesis results on a 28-nm technology show that for a 0.789 M NAND-gates complexity complexity, the architecture reaches a decoding throughput of 0.9 Gbps with 30 decoding iterations. Compared to the 5G binary LDPC code of the same size and code rate, the proposed architecture offers a gain of 0.3 dB at a Frame Error Rate of $$10^{-3}$$ 10 - 3 .

A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures

“…The decoder is capable of achieving 19.5 Gbps [111]. Later, Harb proposed a processing block that updates CNs and their associated VNs in a fully pipelined way, reaching 10.1 Gbps [113].…”

“…The two reported values allow an analysis of the throughput performance and comparison with implementations without SNR and a fixed number of iterations (without early termination). Moreover, the decoders that include early termination [107], [108], [112], [113], [131], only allow for a fair comparison between implementations with the same SNR.…”

“…Designs using the EMS algorithm produce a good performance. This is particularly true for the designs in [111], [113], which amount to one of the best designs in terms of efficiency. Variants that use Trellis schemes for the EMS and MM algorithms achieve results in the same trend and use fewer gates per edge.…”

“…Using a Trellis scheme for MM substantially improves the decoder's performance, placing the implementation on the trend line. For the EMS algorithm, in general the efficiency is excellent, with designs from [113] being among the candidates for the most efficient designs. The exception to the above-average performance is [72] since it uses an old process node technology (180nm).…”

“…In conclusion, designs using Trellis-MM [126] and EMS [113] algorithms are the best performing implementations in terms of area and gate efficiency with the solution from [121], using the IHRB-MLGD algorithm falling short of those designs for lower Galois fields.…”