Ultra-low power and ultra-low voltage devices and circuits for IoT applications

Hiramoto, Toshiro; Takeuchi, Ken; Mizutani, Tomoko; Ueda, Akira; Saraya, Takuya; Kobayashi, Masaharu; Yamamoto, Y.; Makiyama, Hideki; Yamashita, T.; Oda, H.; Kamohara, S.; Sugii, Nobuyuki; Yamaguchi, Yasuo

doi:10.1109/snw.2016.7578025

Cited by 27 publications

(17 citation statements)

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“…Complementary efforts are being invested in the integration of power-efficient technologies and design techniques in wearable systems. Among those are energy-efficient and low-power wireless communication, voltage scaling, low-leakage and low-voltage complementary metal oxide semiconductors [71], and power-performance management.…”

Section: Discussionmentioning

confidence: 99%

Literature on Wearable Technology for Connected Health: Scoping Review of Research Trends, Advances, and Barriers

et al. 2019

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BackgroundWearable sensing and information and communication technologies are key enablers driving the transformation of health care delivery toward a new model of connected health (CH) care. The advances in wearable technologies in the last decade are evidenced in a plethora of original articles, patent documentation, and focused systematic reviews. Although technological innovations continuously respond to emerging challenges and technology availability further supports the evolution of CH solutions, the widespread adoption of wearables remains hindered.ObjectiveThis study aimed to scope the scientific literature in the field of pervasive wearable health monitoring in the time interval from January 2010 to February 2019 with respect to four important pillars: technology, safety and security, prescriptive insight, and user-related concerns. The purpose of this study was multifold: identification of (1) trends and milestones that have driven research in wearable technology in the last decade, (2) concerns and barriers from technology and user perspective, and (3) trends in the research literature addressing these issues.MethodsThis study followed the scoping review methodology to identify and process the available literature. As the scope surpasses the possibilities of manual search, we relied on the natural language processing tool kit to ensure an efficient and exhaustive search of the literature corpus in three large digital libraries: Institute of Electrical and Electronics Engineers, PubMed, and Springer. The search was based on the keywords and properties to be found in articles using the search engines of the digital libraries.ResultsThe annual number of publications in all segments of research on wearable technology shows an increasing trend from 2010 to February 2019. The technology-related topics dominated in the number of contributions, followed by research on information delivery, safety, and security, whereas user-related concerns were the topic least addressed. The literature corpus evidences milestones in sensor technology (miniaturization and placement), communication architectures and fifth generation (5G) cellular network technology, data analytics, and evolution of cloud and edge computing architectures. The research lag in battery technology makes energy efficiency a relevant consideration in the design of both sensors and network architectures with computational offloading. The most addressed user-related concerns were (technology) acceptance and privacy, whereas research gaps indicate that more efforts should be invested into formalizing clear use cases with timely and valuable feedback and prescriptive recommendations.ConclusionsThis study confirms that applications of wearable technology in the CH domain are becoming mature and established as a scientific domain. The current research should bring progress to sustainable delivery of valuable recommendations, enforcement of privacy by design, energy-efficient pervasive sensing, seamless monitoring, and low-latency 5G communications. To comple...

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Section: Discussionmentioning

confidence: 99%

Literature on Wearable Technology for Connected Health: Scoping Review of Research Trends, Advances, and Barriers

et al. 2019

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“…For example, it is a great requirement for ultralow-power logic units for portable devices and processing massive data. [1][2][3] However, when the conventional silicon-based field-effect transistors (FETs) enter the sub-5 nm process node, the channel length and the gate dielectric thickness are only of nanometers, making the applications. [29][30][31][32] Up to now, WSe 2 based P-type NC-FETs have been successfully obtained through engineering the electrical contact.…”

Section: Introductionmentioning

confidence: 99%

WSe₂ N‐Type Negative Capacitance Field‐Effect Transistor with Indium Low Schottky Barrier Contact

Dong

Sheng

et al. 2021

Adv Elect Materials

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carrier mobility of the semiconductor channel drop sharply, the electrostatic gate control ability weak and the short channel effect prominent. [4][5][6] In such a case, the subthreshold slope (SS) of the devices will increase and the leakage current will become impressive, leading to non-negligible static power consumption. Therefore, it is very necessary to exploit new device structures and channel materials to effectively lower the SS and enhance the gate control ability to meet the needs of the low power consumption.As one of the emerging device structures, negative capacitance field-effect transistor (NC-FET) has attracted much attention. [7][8][9] It is achieved with a ferroelectric field-effect transistor (FeFET) device configuration, in which the dielectric is replaced by ferroelectric materials. The negative capacitance is realized by the polarization switch of the ferroelectric dielectric, which gives a chance to get steep SS to overcome the limit of 60 mV dec −1 (at room temperature) dominated by the Boltzmann distribution. [10][11][12] Up to now, many ferroelectric materials like organic poly(vinylidene difluoride-trifluoroethylene) [P(VDF-TrFE)] [13,14] and inorganic perovskite lead zirconate titanate (PZT) [15,16] have been successfully applied to NC-FETs. Recently, the discovery of ferroelectricity in Hf x Zr 1−x O 2 (HZO) further promotes the development in this field for its scalable thickness and compatibility with commercial semiconductor technology. [17][18][19] HZO has been currently applied to NC-FETs and shows the possibility to lower the SS far less than 60 mV dec −1 , indicating great potential for low-power integrated electronics. [18] To continue the effective electrostatic control in field-effect transistors (FETs), the channel semiconductor thickness should be less than the electrostatic screening length and one-third of the gate length. [20,21] On this point, 2D layered semiconductors are of obvious advantages, [22][23][24][25][26] which are the thinnest crystals (typically less than 1 nm) with excellent electronic properties, providing a possibility to push down the device feature size to even less than 3 nm without the loss of electrostatic control ability. [27,28] Among various 2D layered materials, ambipolar 2D semiconductors, like WSe 2 , are promising for electronic circuit design because of that both P-type and N-type transistors can be achieved in the same layer and easily homogeneously integrated for complementary metal oxide semiconductor (CMOS)

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“…The continuous scaling of transistor sizes and technology advances are driving the demand for low power portable devices [33,58]. The International Data Corporation (IDC) [3] estimates that there will be 41.6 billion devices connected to the Internet, generating 79.4 zettabytes (ZB) of data in 2025.…”

Section: Introductionmentioning

confidence: 99%

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

Tsiokanos

Miskelly

et al. 2021

J. Emerg. Technol. Comput. Syst.

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In recent years, physical unclonable functions (PUFs) have gained a lot of attention as mechanisms for hardware-rooted device authentication. While the majority of the previously proposed PUFs derive entropy using dedicated circuitry, software PUFs achieve this from existing circuitry in a system. Such software-derived designs are highly desirable for low-power embedded systems as they require no hardware overhead. However, these software PUFs induce considerable processing overheads that hinder their adoption in resource-constrained devices. In this article, we propose DTA-PUF, a novel, software PUF design that exploits the instruction- and data-dependent dynamic timing behaviour of pipelined cores to provide a reliable challenge-response mechanism without requiring any extra hardware. DTA-PUF accepts sequences of instructions as an input challenge and produces an output response based on the manifested timing errors under specific over-clocked settings. To lower the required processing effort, we systematically select instruction sequences that maximise error-rate. The application to a post-layout pipelined floating-point unit, which is implemented in 45 nm process technology, demonstrates the effectiveness and practicability of our PUF design. Finally, DTA-PUF requires up to 50× fewer instructions than existing software processor PUF designs, limiting processing costs and resulting in up to 26% power savings.

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Ultra-low power and ultra-low voltage devices and circuits for IoT applications

Cited by 27 publications

References 0 publications

Literature on Wearable Technology for Connected Health: Scoping Review of Research Trends, Advances, and Barriers

Literature on Wearable Technology for Connected Health: Scoping Review of Research Trends, Advances, and Barriers

WSe₂ N‐Type Negative Capacitance Field‐Effect Transistor with Indium Low Schottky Barrier Contact

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

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Ultra-low power and ultra-low voltage devices and circuits for IoT applications

Cited by 27 publications

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Literature on Wearable Technology for Connected Health: Scoping Review of Research Trends, Advances, and Barriers

Literature on Wearable Technology for Connected Health: Scoping Review of Research Trends, Advances, and Barriers

WSe2 N‐Type Negative Capacitance Field‐Effect Transistor with Indium Low Schottky Barrier Contact

DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices

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WSe₂ N‐Type Negative Capacitance Field‐Effect Transistor with Indium Low Schottky Barrier Contact