Ultra-Low-Power Class-AB Bulk-Driven OTA with Enhanced Transconductance

Choe, Seong Jin; Lee, Ju Sang; Park, Sung Sik; Yu, Sang Dae

doi:10.1587/transele.2018ecs6002

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…Quasi-floating gate requires a high value resistor, R Large , typically implemented by a single transistor connected to a DC biasing voltage and a capacitor, C i , connected to the AC input voltage in order to work properly. Low voltage analog circuits have been widely improved by using these Bulk Driven [4,5,6,7,8,9,10,11,12,13,14,15,16] and Floating Gate [17,18,19,20,21,22,23,24,25,26,27,28,29,30] techniques, and from them we derive the new technique presented in following section.…”

Section: Introductionmentioning

confidence: 99%

Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

Molina-R

Gurrola

Padilla

et al. 2020

IEICE Electron. Express

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This letter details a novel floating-bulk transistor technique for low-voltage design. The approach is derived from two previous wellknown techniques: bulk-driven and quasi floating-gate. The floating-bulk technique uses an input capacitive coupling through a floating bulk of a PMOS allowing modulation of the drain current. A fabricated commonsource amplifier was tested on CMOS 0.5 µm technology and the feasibility of the proposal was demonstrated.

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Section: Introductionmentioning

confidence: 99%

Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

Molina-R

Gurrola

Padilla

et al. 2020

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Sub-threshold based designs addresses ultrasonic, biomedical, and wireless sensor interface applications [5,[10][11][12][13][14][15]. The obstacle with design of low power analog circuits is relatively high threshold voltages, which is the result of scaling difference between the power supply and the threshold voltage (Vt).…”

Section: Introductionmentioning

confidence: 99%

Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology

Afacan

2020

Sakarya University Journal of Science

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The requirement of low-power analog circuits has been raised in recent years due to the strict limitation of power consumption in modern applications. Therefore, the trend in analog circuit design has been changed such that they are able to meet the required specifications with lower power dissipation. Design of low power operational transconductance amplifiers, which are the main building blocks in many analog applications, has been more pronounced to keep the power dissipation below certain levels. In this concern, this study presents a low power, highperforming bulk-driven 3 stages CMOS OTA in a 130 nm standard CMOS technology. The proposed circuit leverages the bulk-driven architecture at the input stage; thus it can operate under sub 1-V. The design process of the proposed OTA is explained in detail and the results are validated via post-layout simulations. The proposed OTA is powered by ±0.45 V symmetric voltage sources, where the power consumption is around 27 μW. The area overhead is only 0.0017 μm2. The open-loop gain, unity gain frequency, and the phase margin are 73.24 dB, 5.167 MHz, and 78 o , respectively. To demonstrate the performance of the proposed circuit, a comparison is made with other circuits published in the last five years considering the well-known figures of merit (FOMs). Comparison results indicate that the proposed solution outperforms the other circuits for small-signal operation while it is the runner-up for large-signal operation.

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Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels

Padilla-Cantoya

Gurrola-Navarro

Bonilla-Barragan

et al. 2022

IEICE Electron. Express

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A four-quadrant analog multiplier with ultra-low supply voltage operation, rail-to-rail input swing and insensitive to different dc levels between the multiplied input signals is presented. It is based on the Floating-Bulk technique, in which the input signal is coupled to the bulk terminal of a PMOS transistor by means of an input capacitor. This allows rail-to-rail operation and eliminates the dc level of the input signals regardless of the offset between them, maintaining linearity. Moreover, it also eliminates the threshold-voltage requirement in the signal path of the input transistors, allowing very low voltage operation defined by a gate-source and a drain-source voltages. Experimental results in 0.5µm technology demonstrate rail-to-rail operation with a 1.1 V supply voltage even with different dc level voltages between the multiplied input signals. It offers a distortion of THD = 0.95 % for an input signal of 0.2Vpp at 100kHz.

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Ultra-Low-Power Class-AB Bulk-Driven OTA with Enhanced Transconductance

Cited by 3 publications

References 7 publications

Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology

Four-quadrant multiplier using the floating-bulk technique for rail-to-rail input range and insensitivity to different input dc levels

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