2020 IEEE Custom Integrated Circuits Conference (CICC) 2020
DOI: 10.1109/cicc48029.2020.9075938
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Ultra-Low Power Receivers for IoT Applications: A Review

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Cited by 24 publications
(8 citation statements)
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“…However, such improvement comes at the cost of power and area due to multiple receiver paths and DSP blocks. Implementing the DSP in an advanced CMOS process with optimal number of bits and FFT points [2], [8] and using low-power receivers [14] would lower the power consumption significantly. On-chip power splitters and oscillator pulling [15] might provide a challenge that should be further explored for realizing single chip implementation of multi-receiver XC.…”
Section: Discussionmentioning
confidence: 99%
“…However, such improvement comes at the cost of power and area due to multiple receiver paths and DSP blocks. Implementing the DSP in an advanced CMOS process with optimal number of bits and FFT points [2], [8] and using low-power receivers [14] would lower the power consumption significantly. On-chip power splitters and oscillator pulling [15] might provide a challenge that should be further explored for realizing single chip implementation of multi-receiver XC.…”
Section: Discussionmentioning
confidence: 99%
“…Contrary to commercial transceivers with integrated RF circuits, the RF front-end and the low-noise preamplifier in our setup are off-the-shelf components that are not optimized for low-power operation. The Myriad RF board has a typical power consumption of 725 mW in Rx [22], whereas recent integrated LPWAN transceivers feature power budgets in the 1-10 mW range [9]. Since this work focuses only on the digital signal processing, and not on the RF front-ends that often dominate the power budgets, we ignore the nonoptimized low-noise preamplifier and RF front-end from the power measurements and include only the DFE and DBB.…”
Section: B Minimum Cpu Frequency and Energy Consumptionmentioning
confidence: 99%
“…Yet, the main challenge of SDRs for IIoT sensors is to execute the DBB processing in software with a power consumption that fits in the 1-10 mW budget of LPWAN transceivers [9]. Three different approaches have been identified in the literature to tackle this challenge.…”
Section: Introductionmentioning
confidence: 99%
“…If a design can suffice without the reconfigurability, low non-recurring engineering costs, and shorter development times offered by FPGAs, then a custom ASIC may prove to be to a better alternative. For more information on ASICs in IoT networks, we encourage the reader to refer to references [ 92 , 93 , 94 ].…”
Section: Mid-range Iot Solutionsmentioning
confidence: 99%