Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

Abstract

An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

“…Laterally diffused metal-oxide semiconductor (LDMOS) field-effect transistors (FETs) are commonly used for lowvoltage (< 30 V) [1][2][3][4], mid-voltage (30 V -100 V) [5][6][7], and high-voltage (> 100 V) [8,9] power applications. Many novel LDMOS device technologies with different device configurations have been proposed recently to achieve a better figure-of-merit (FOM = BV 2 /Ron), i.e., a high breakdown voltage (BV) with a low on-resistance (Ron), for different practical voltage ranges [10][11][12][13][14]. However, complex device structures are often introduced in these proposed technologies which make the industrial fabrication process very difficult and costly.…”