Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

Huang, Chi-Ray; Wu, Kuan‐Lin; Wu, Congyi; Chiou, Lih-Yih

doi:10.1109/iscas.2018.8350944

Cited by 11 publications

(2 citation statements)

References 11 publications

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“…Although a conventional 6-T SRAM cell occupies the smallest area, it has a small read static noise margin (RSNM) because the read and write operations are through the same BL/BLB pair. The small RSNM makes it susceptible to read disturbance, particularly during the CIM operation because multiple SRAM cells on the same BL may be read simultaneously [43], [44], [45]. The read-decoupled eight-transistor (RD8T) SRAM cell shown in Fig.…”

Section: Proposed Low-leakage 8-t Sram Cellmentioning

confidence: 99%

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

Chen,

Dai,

Hong

2024

IEEE Trans. VLSI Syst.

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This article demonstrates the first functional neuromorphic spiking neural network (SNN) that processes the time-to-first-spike (TTFS) encoded analog spiking signals with the second-order leaky integrate-and-fire (SOLIF) neuron model to achieve superior biological plausibility. An 8-kb SRAM macro is used to implement the synapses of the neurons to enable analog computing in memory (ACIM) operation and produce current-type dendrite signals of the neurons. A novel lowleakage 8T (LL8T) SRAM cell is proposed for implementing the SRAM macro to reduce the read leakage currents on the read bitlines (RBLs) when performing ACIM. Each neuron's soma is implemented with low-power analog circuits to realize the SOLIF model for processing the dendrite signals and generating the final analog output spikes. No data converters are required in our design by virtue of analog computing's nature. A test chip implementing the complete output layer of the proposed SNN was fabricated in 90-nm CMOS. The active area is 553.4 × 118.6 µm 2 . The measurement results show that our SNN implementation achieves an average inference latency of 196 ns and an inference accuracy of 81.4%. It consumes 242 µW with an energy efficiency of 4.74 pJ/inference/neuron.

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Section: Proposed Low-leakage 8-t Sram Cellmentioning

confidence: 99%

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

Chen,

Dai,

Hong

2024

IEEE Trans. VLSI Syst.

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“…x m,off (t) is defined in the same way for Q m,off (t). Besides, the computation results from the BS are usually of small size [42]- [44], and the standby power accounts for a relatively small proportion of overall power consumption by standby power management techniques such as autonomous normallyoff power transition [45], adaptive data retention voltage regulating scheme [46], and power-gating and source bias design technique [47]. Therefore, by neglecting the power consumption of downlink reception and standby mode on devices, the total power consumption can be given by…”

Section: Computation Modelmentioning

confidence: 99%

Online Offloading Scheduling for NOMA-Aided MEC Under Partial Device Knowledge

Hua,

Tian,

Lyu

et al. 2021

Preprint

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By exploiting the superiority of non-orthogonal multiple access (NOMA), NOMA-aided mobile edge computing (MEC) can provide scalable and low-latency computing services for the Internet of Things. However, given the prevalent stochasticity of wireless networks and sophisticated signal processing of NOMA, it is critical but challenging to design an efficient task offloading algorithm for NOMA-aided MEC, especially under a large number of devices. This paper presents an online algorithm that jointly optimizes offloading decisions and resource allocation to maximize the long-term system utility (i.e., a measure of throughput and fairness). Since the optimization variables are temporary coupled, we first apply Lyapunov technique to decouple the long-term stochastic optimization into a series of per-slot deterministic subproblems, which does not require any prior knowledge of network dynamics. Second, we propose to transform the non-convex per-slot subproblem of optimizing NOMA power allocation equivalently to a convex form by introducing a set of auxiliary variables, whereby the time-complexity is reduced from the exponential complexity to O(M 3/2 ). The proposed algorithm is proved to be asymptotically optimal, even under partial knowledge of the device states at the base station. Simulation results validate the superiority of the proposed algorithm in terms of system utility, stability improvement, and the overhead reduction.

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Stability and Power Analysis of Read Decoupled 8T SRAM Cell

Bansal

Tomar

2021

Advances in Intelligent Systems and Computing

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Ultra-Low Standby Power SRAM with Adaptive Data-Retention-Voltage-Regulating Scheme

Cited by 11 publications

References 11 publications

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM

Online Offloading Scheduling for NOMA-Aided MEC Under Partial Device Knowledge

Stability and Power Analysis of Read Decoupled 8T SRAM Cell

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