Ultra-scaled MoS₂ transistors and circuits fabricated without nanolithography

Abstract

The future scaling of semiconductor devices can be continued only by the development of novel nanofabrication techniques and atomically thin transistor channels. Here we demonstrate ultra-scaled MoS2 field-effect transistors (FETs) realized by a shadow evaporation method which does not require nanofabrication. The method enables large-scale fabrication of MoS2 FETs with fully gated ∼10 nm long channels. The realized ultra-scaled MoS2 FETs exhibit very small hysteresis of current–voltage characteristics, high drain currents up to ∼560 A m−1, very good drain current saturation for such ultra-short devices, subthreshold swing of ∼120 mV dec−1, and drain current on/off ratio of ∼106 in air ambient. The fabricated ultra-scaled MoS2 FETs are also used to realize logic gates in n-type depletion-load technology. The inverters exhibit a voltage gain of ∼50 at a power supply voltage of only 1.5 V and are capable of in/out signal matching.

Edge-Contact MoS2 Transistors Fabricated Using Thermal Scanning Probe Lithography

“…Then, wet etching in diluted TMAH for 2 min was used to open the PMGI, controlling the undercut for the subsequent lift-off. TMAH can fully remove PMGI without deteriorating the 2DM, as reported in previous studies. , …”

High Current Density in Monolayer MoS2 Doped by AlOx

“…(b) Maximum I on vs I on / I off of our AlO x -doped MoS 2 compared with other doped 2D-FETs. ,,,,− While some doping methods yield high I on , the I on / I off can be much lower due to charge trapping in the 2D material or its interface. (c) Benchmarking of monolayer MoS 2 transistor I on vs channel length ( L ) at V DS = 1 V. ,,,,− Also shown are IRDS high-performance (HP) and low-power (LP) metrics at V DS = 0.75 V and 10–20 nm gate lengths . The simple model (solid lines) estimates achievable I on with R C = 480 Ω·μm (this work) or 1 kΩ·μm.…”

Secure Electronics Enabled by Atomically Thin and Photosensitive Two-Dimensional Memtransistors

“…Atomically thin 2D layered semiconductors such as transition-metal dichalcogenides (TMDCs) are ∼10× thinner at their monolayer limit (∼0.7 nm) compared to state-of-the-art silicon fin structures (∼6 nm) and promise to offer better channel-to-dielectric interfaces owing to the absence of dangling bonds in transistor geometries. Recent report of scalable fabrication of ultrascaled transistors ( L CH ∼ 10 nm) on chemical vapor deposition (CVD) grown MoS 2 with considerably low hysteresis, high ON current (∼560 A/m), and low subthreshold swing (∼120 mV/dec) shows good promise in order to meet the requirements set forth by the International Roadmap of Devices and Systems (IRDS) . A long-standing concern on high contact resistance of 2D transistors has also been mitigated earlier this year for MoS 2 .…”