Ultra-steep-slope transistor enabled by an atomic memristive switch

Cheng, Bojun; Emboras, Alexandros; Passerini, Elias; Lewerenz, Mila; Eppenberger, Marco; Zumtaugwald, Samuel; Ducry, Fabian; Aeschlimann, Jan; Tiwari, Sandip; Luisier, Mathieu; Leuthold, Juerg

doi:10.1117/12.2566679

Cited by 1 publication

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“…It acts as a basic low-leakage circuit element and constitutes a memristive nFET. The TS device features a top electrode that has a unique 3-D tip to confine the memristive operation and limit the leakage current to the tip apex [10]. Fig.…”

Section: Low-leakage Threshold Switchmentioning

confidence: 99%

“…The parameters of the standard and lower-switching threshold TS are given in Table I. It is worth noting that both models are based on experimentally demonstrated TS devices we fabricated [10], [14]. In addition, V th is adjusted to best match V DD .…”

Section: Memristive Circuits For Near-thresholdmentioning

confidence: 99%

“…As an alternative to PCMs, filament-based threshold switching (TS), also known as conductive bridging random access memory (CBRAM)-type memristors [7], [8], offer steep switching, low switching voltage, low energy consumption, high ON/OFF ratios, and small footprint. Hybrid-FETs with filament-based TS have been demonstrated with an SS below 5 mV/decade [9], [10].…”

Section: Introductionmentioning

confidence: 99%

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Threshold Switching Enabled Sub-pW-Leakage, Hysteresis-Free Circuits

Cheng

Emboras

Passerini

et al. 2021

IEEE Trans. Electron Devices

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In this article, we present ultralow leakage logic circuits by combining 3-D memristors with CMOS transistors. Significant leakage current reductions of up to 99% are found by experiments and simulation for a memristive hybrid-inverter if compared with a conventional inverter. Likewise, circuit simulations of memristive hybrid ring oscillators, NAND, or full adders show more than 100% gain in energy efficiency per cycle over state-ofthe-art circuits. Importantly, the memristive circuits offer hysteresis-free operation. The hysteresis-free operation is due to properly engineered properties-such as the threshold voltage-of the memristors to match the circuit, as well as the self-adaptive filament diameter of our memristor during operation. Lastly, the memristors feature a 10 8 ON-OFF ratio, enabling both high speed and low leakage (∼10 fA) when integrated with a transistor. They also come with a well-controlled filament formation on a ∼10-nm footprint, making them ideal to integrate with modern CMOS technology transistors.

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Section: Low-leakage Threshold Switchmentioning

confidence: 99%

Section: Memristive Circuits For Near-thresholdmentioning

confidence: 99%