Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates

Lotze, Niklas; Manoli, Yiannos

doi:10.1109/tcsi.2017.2705053

Cited by 42 publications

(19 citation statements)

References 31 publications

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“…Figure2 also overcomes all clock overlap issues that were recognized in the existing circuits.Table 1. Shows the results of different CMOS technologies for the existing circuit [10], [16].…”

Section: Figure 2 Tspc Det-ff With Tg-muxmentioning

confidence: 99%

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

Prabhakar¹,

Naresh²,

Krishna³

et al. 2021

TURCOMAT

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The paper outlines the utmost importance of energy-efficient devices for IoT applications and recommends adual edge-triggeredTSPC flip-flop in fully-static mode at 45nm technology with low supply rail carried out in CMOS using MENTOR GRAPHICS tool.The proposed flip-flop proved to be energy efficient compared to traditional double and single edge-triggered flip-flops in terms of latency, power, the figure of merit and area for IoT applications. A comparison of two types of dual-edge triggered flip-flops are analyzed concerning the mentioned performance metrics and deduces the best flip-flop for IoT applications. Clock overlap issues are turning down in dual edge-triggered TSPC flip-flopcompared with a conventional dual edge-triggered flip-flop in full static modeand allow stringent operation at 1V supply rail thatdelivers1.14uW power, 0.60fJ figure of merit and 531.99ps latency at 45nm CMOS

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Section: Figure 2 Tspc Det-ff With Tg-muxmentioning

confidence: 99%

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

Prabhakar¹,

Naresh²,

Krishna³

et al. 2021

TURCOMAT

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“…For a constant W/L and

is exponentially dependent on

, having much smaller value in comparison to the drain current in saturation or strong inversion region. The sub-threshold operation of a transistor is illustrated in [ 46 , 47 , 48 , 49 ].…”

Section: Low Power Design Techniques Used For the Analog Designmentioning

confidence: 99%

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Bhattacharyya

Gruenwald

Jansen

et al. 2018

Sensors

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Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μm CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 normalmm2. The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μW. The analog part of the design consumes only 36 μW, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches.

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“…A vivid description about sub-threshold operation is provided in [27][28][29]. For the design of the analog part, weak-inversion region of operation is used extensively which is discussed in detail for some of the circuits.…”

Section: Analog Power Consumptionmentioning

confidence: 99%

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

Bhattacharyya

Gruenwald

Jansen

et al. 2018

JLPEA

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Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 µm CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 µW. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD).

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Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates

Cited by 42 publications

References 31 publications

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

Design and Analysis of FS-TSPC-DET Flip-Flop for IoT Applications

An Ultra-Low-Power RFID/NFC Frontend IC Using 0.18 μm CMOS Technology for Passive Tag Applications

Design of a Programmable Passive SoC for Biomedical Applications Using RFID ISO 15693/NFC5 Interface

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