Ultra-Thin Film SOI/BOX Substrate Development, Its Application and Readiness

Abstract

The Ultra-Thin SOI and BOX substrates are the foundation of Fully Depleted planar technology, a CMOS scaling solution for 20 nm node and beyond. Using the Smart CutTM technology, UTSOI substrates development, with SOI & BOX thickness reduced down to 12 & 25 nm respectively, is on the way to High Volume Manufacturing by the end of 2011. To improve device Vt variation control, SOI total layer thickness variation of less than +/- 1 nm for all the measured points and all the preproduction wafers is already achieved and +/- 0.5 nm variation is targeted. Tight SOI thickness variation at device scale and BOX thickness variation are also demonstrated.

Ultra-Thin SOI/BOX Layers and Next Generations Planar Fully Depleted Substrates

“…Figure 6 describes introduction roadmap of this continuum of substrate options, from high volume manufactured UTBOX25 to UTBOX10 and sSOI which are already available for sampling from development lines. SOI & BOX thickness variation roadmaps are defined for all substrate options taking into account device V T variability requirement for next technology nodes and available results demonstrate, according to product maturity, similar possibilities than UTBOX25 (6). Device scale SOI thickness variation, monitored through micro-roughness measurement, already exhibit significant improvement on UTBOX10 and sSOI substrates.…”

“…However, silicon thickness itself appears as a new source of V T variation, with empirical correspondence close to 25mV/nm (3). Accordingly, T Si maximum fluctuation of 1nm is set as an objective for FDSOI substrates (4).…”

SiGe and Ge on Insulator Wafers

“…Initial SOI layer thickness range. Based on today available wafers: 0.4nm is the best wafers, 0.8nm is typical for high uniformity substrates [8].…”

“…Figure 1 shows a SOI layer thickness map with a range of 0.41nm. FDSOI availability is described in details by Schwarzenbach et al [8].…”

Silicon on Insulator with Highly Uniform Top Si Fabricated by H/He Coimplantation*

“…[12] However, the influence of H/He co-implantation on the transferred silicon film thickness uniformity is seldom reported. As the requirement of silicon film thickness uniformity has reached ±5 Å for the fabrication of FD-SOI, [14] it is of great significance to explore a layer transfer method to achieve highly uniform top silicon.…”