Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Jooq, Mohammad Khaleqi Qaleh; Ahmadinejad, Mohammad; Moaiyeri, Mohammad Hossein

doi:10.1002/cta.2876

Cited by 15 publications

(7 citation statements)

References 37 publications

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“…Finally, the gate metal is deposited over the gate dielectric. More details regarding the fabrication process of FinFETs can be found in [22], [23].…”

Section: A 7nm Finfet Technologymentioning

confidence: 99%

High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology

Jooq,

Azghadi,

Behbahani

et al. 2023

IEEE Access

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In designing neuromorphic circuits and systems, developing compact and energy-efficient neuron and synapse circuits is essential for high-performance on-chip neural architectures. Toward that end, this work utilizes the advanced low-power and compact 7nm FinFET technology to design leaky integrateand-fire (LIF) neuron and spike-timing-dependent plasticity (STDP) circuits. In the proposed STDP circuit, only six FinFETs and three small capacitors (two 10fF and 20fF) have been utilized to realize STDP learning. Moreover, 12 transistors and two capacitors (20fF) have been employed for designing the LIF neuron circuit. The evaluation results demonstrate that besides 60% area saving, the proposed STDP circuit achieves 68% improvement in total average power consumption and 43% lower energy dissipation compared to previous works. The proposed LIF neuron circuit demonstrates 34% area saving, 46% power, and 40% energy saving compared to its counterparts. The neuron can also tune the firing frequency within 5MHz-330MHz using an external control voltage. These results emphasize the potential of the proposed neuron and STDP learning circuits for compact and energy-efficient neuromorphic computing systems.

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“…Finally, the gate metal is deposited over the gate dielectric. More details regarding the fabrication process of FinFETs can be found in [22], [23].…”

Section: A 7nm Finfet Technologymentioning

confidence: 99%

High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology

Jooq,

Azghadi,

Behbahani

et al. 2023

IEEE Access

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“…They are considered one of the critical components when it comes to performance in various kinds of Embedded Components, Digital Signals Processors, and Logical Units that execute different applications such as image processing, arithmetic, and filtering. Therefore, several research studies have been done to enhance the multiplication operation in order to improve the speed, the power consumption [Khaleqi Qaleh Jooq et al, 2021][Mounica et al, 2021, as well as the area [Sakthimohan and Deny, 2021]. Likewise, the pace of modern equipment has been increased, so the demand for highperformance systems has been rocketed [Seferlis et al, 2021].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

Al-Nounou¹,

Al-Khaleel²,

Obeidat³

et al. 2022

jucs

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

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“…In the VLSI design, the optimization is accomplished from the device level to the system level. While employing the optimization techniques at the system level, some inexactness or inaccuracy is acceptable 1–3 . Due to the introduction of small inaccuracy, the power consumption, area, and performance of the system can be upgraded to a great extent.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, two novel error‐tolerant compressors are illustrated in Edavoor et al 14 The area, power, and delay parameters are improved with an error rate of 25% using approximate multipliers. Efficient approximate multipliers are explained using novel compressor circuits at the transistor level by Khaleqi et al 1 The eight transistor‐based 4:2 compressor is recommended to reduce the power and area to the utmost level, but this approximate compressor produces more error than exact compressor. In the same work, another superior imprecise multiplier is introduced using 24 transistor‐based compressors with tolerable error.…”

Section: Introductionmentioning

confidence: 99%

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

Odugu

C²,

2021

Circuit Theory & Apps

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The very large‐scale integration (VLSI) design‐based architectures of 2‐D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2‐D digital filters. In this work, circular symmetry is adopted to optimize the 2‐D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal‐oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2‐D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2‐D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45‐nm CMOS technology. The final physical design layout‐area, power, and delay reports are correlated with existing state‐of‐artworks. It is found that the proposed 2‐D FIR filter outperforms the existing works.

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Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Cited by 15 publications

References 37 publications

High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology

High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

An efficient VLSI architecture of 2‐D finite impulse response filter using enhanced approximate compressor circuits

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