In this paper, a lateral power metal–oxide–semiconductor field‐effect transistor with ultra‐low specific on‐resistance is proposed to be applied to a high‐voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt‐implanted p‐drift layer assists in the full depletion of the n‐drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n‐drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in Ron.sp and a 16% improvement in BV.