Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Abstract

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%.

Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs

“…6 shows the schematic of the considered STT-MRAM bitcell, which includes the access transistor and the storage element, typically placed between the second and fourth metal layers (M2 and M4) [32]. Among the different DMTJ-based bitcell topologies, here we refer to the one transistor-one DMTJ in standard connection (i.e., 1T1DMTJ-SC where the minimum-sized access transistor is connected to the RL T ), which allows the best trade-off between area and energy [31,33].…”

Performance Benchmarking of TFET and FinFET Digital Circuits from a Synthesis-Based Perspective

“…Alternative device concepts based on different operating principles and semiconductor materials are required to deal with the above challenges [15]. The FinFET device has been proposed as an alternative to bulk CMOS technology nodes below 32 nm thanks to its superior scalability, lower gate leakage current, and a better control over short-channel effects [16][17][18]. However, FinFET and bulk CMOS devices share thermionic emission as a main mechanism of conduction, which limits their subthreshold slope (SS) to 60 mV/dec at room temperature [19][20][21].…”

Distribution of write error rate of spin-transfer-torque magnetoreistive random access memory caused by a distribution of junction parameters

“…Spin-transfer-torque magnetoreistive random access memory (STT MRAM) has been attracting much attention as a key component for future low-power electronics because of its useful characteristics such as high integration density, non-volatility, low-latency, and high-endurance [1][2][3][4][5][6][7][8][9]. In STT MRAM information is written as stable magnetic states which are separated by energy barrier due to magnetic anisotropy by using the STT switching method [10][11][12].…”