UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC

Shah, Mehul A.; Barren, J.; Brooks, Jeffrey; Golla, Robert; Grohoski, Greg; Gura, Nils; Hetherington, R.C.; Jordan, Paul L.; Luttrell, M.; Olson, Charles; Sana, B.; Sheahan, Denis; Spracklen, Lawrence; Wynn, Allen

doi:10.1109/asscc.2007.4425786

Cited by 78 publications

(17 citation statements)

References 1 publication

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“…Current methodologies and computing power are not sufficient enough to surpass this bottleneck [22]. However, many manufacturers provide multicore processors and/or prototypes to achieve the high performance computation like Intel Terascale Processors [45] or Microsystems UltraSPARC T2 [64].…”

Section: Bioinformatics Applicationsmentioning

confidence: 99%

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Zahid

Khurshid

Memon

2018

ITC

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With the increasing need of computational power the trend towards multicore processors is ubiquitous. The current on-chip architecture comprises multiple cores which usually share last level cache which can be physically distributed on chip. In order to provide system predictability, especially for a real time system where quality of service (QoS) depends on minimum miss rates and low worst case execution time (WCET) for applications running on different cores, efficient cache management techniques are required. Since memory hierarchy and its management is the key of overall system performance and access to off-chip memory for data consumes many clock cycles along with many units of power it is important to restrict the off-chip access and provide the optimum solution for the on-chip access. To increase performance and energy efficiency, various techniques are proposed. This article aims to provide the researchers with the state-of-the-art critical review of the various approaches that focus on data replication and cache partitioning techniques for L3 cache. The existing literature is presented through several classifications based on appropriate design and algorithm. Maintaining energy efficient system is a crucial challenge for multicore processors. We have discussed various techniques which address upscaling performance without compromising on energy efficiency. Lastly, different literature work is discussed where authors evaluate cache and/or various processors for high performance applications such as bioinformatics, image and video processing, IOT applications and applications using DSP processors.

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Section: Bioinformatics Applicationsmentioning

confidence: 99%

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Zahid

Khurshid

Memon

2018

ITC

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“…The work on computer systems based on silicon photonic interconnects has been reported [3]. The ever growing complexity, computation and communication requirements of military & commercial applications continue to drive the need for scaling high performance computer systems.…”

Section: Silicon Photonics and Vlsi Electronics For Computing Sysmentioning

confidence: 99%

Challenges in Integration of Microelectronics & Photonics with Nano-chemistry

Ahmad¹,

Sattar²,

Ali³

2017

International Journal of Advanced Research in Computer and Comm

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Electronics, in particular VLSI technology, has made possible design of sophisticated, complex and powerful systems for user. Although silicon technology is evolving continuously to produce smaller, faster and reliable systems with low power, eventually the integration of Microelectronics and Photonics with Nano-chemistry as the driving force is the new area of research that spans from environmental management , smart health-care, smart energy management to new innovations in communications, processing and man-machine interfaces. This has created tremendous opportunities for realization of new systems. The co-existence of silicon technology with these emerging technologies, photonics and nano-chemistry has created new design opportunities for the designer, bringing new challenges to be solved. In this paper, some of the important challenges have been discussed.

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“…The vast majority of today's homogeneous chips [32][23][34] [7], including homogeneous chips with vector units [31], tightly couple the cores with hardware-implemented, fine-grained, cachecoherent shared virtual memory (CCSVM). The virtual memory is managed by the operating system's kernel and easily shared between threads.…”

Section: Homogeneous Multicore Chipsmentioning

confidence: 99%

Evaluating cache coherent shared virtual memory for heterogeneous multicore chips

Hechtman

Sorin

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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The trend in industry is towards heterogeneous multicore processors (HMCs), including chips with CPUs and massively-threaded throughput-oriented processors (MTTOPs) such as GPUs. Although current homogeneous chips tightly couple the cores with cache-coherent shared virtual memory (CCSVM), this is not the communication paradigm used by any current HMC. In this paper, we present a CCSVM design for a CPU/MTTOP chip, as well as an extension of the pthreads programming model, called xthreads, for programming this HMC. Our goal is to evaluate the potential performance benefits of tightly coupling heterogeneous cores with CCSVM.

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UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC

Cited by 78 publications

References 1 publication

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Challenges in Integration of Microelectronics & Photonics with Nano-chemistry

Evaluating cache coherent shared virtual memory for heterogeneous multicore chips

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