Ultrathin InAs nanowire growth by spontaneous Au nanoparticle spreading on indium-rich surfaces

Abstract

Ultrathin InAs nanowires (NWs) can enable true one-dimensional electronics. We report a growth phenomenon where a bimodal size distribution (∼ α nm and ∼ 5 nm in diameter) of InAs NWs can be achieved from gold (Au) nanoparticles of a single size, α (α = 50-250 nm). We determine that ultrathin InAs NW growth is seeded by ultra-small Au nanoparticles shed from the large Au seeds upon indium (In) introduction into the growth system and formed prior to the supersaturation of In in Au. The Au spreading phenomenon is explained by the balancing of Gibbs free energy lowering from In-Au mixing and the surface tension increase. Ultrathin InAs NWs formed in this way exhibit a perfect wurtzite structure with no stacking faults. We have observed InAs NWs with diameters down to ∼ 2 nm using our growth method. Passivating the ultrathin InAs NWs with an AlAs shell, subsequently oxidized in air, results in physical deformation of the InAs core, demonstrating the mechanical pliability of these ultrathin NWs.

Ultrathin catalyst-free InAs nanowires on silicon with distinct 1D sub-band transport properties

“…To date, the realization of ultrathin (~sub-30 nm) InAs NWs was primarily achieved by vapor-liquid-solid (VLS) growth processes using foreign catalysts, amongst which gold (Au) [11][12][13][14][15][16][17] and other metals such as Ag [18] and Ni [19] have been used. A common problem encountered in direct growth from metal catalysts is the typically large diameter and length distribution [13][14][15][16][17][18][19] and non-epitaxial growth [13,18,19]. In addition, Au catalysts, which are most heavily used, are incompatible with Si-based CMOS technology due to deep level traps they form in the band gap of Si [20].…”

Effect of strain and diameter on electronic and charge transport properties of indium arsenide nanowires

“…By doing so we obtain an effective mass of 0.023 in good agreement with effective mass of 0.026 from ref. [19]. For all nanowire calculations, a Monkhorst-Pack sampling 29 with a 23×1×1 k-point grid and energy cut-off of 100 Hartree is used to generate the real-space grid and for bulk calculations a 13×13×13 k-point grid were used.…”

Influence of Surface Passivation on Indium Arsenide Nanowire Band Gap Energies

“…As a transistor's channel becoming increasingly smaller, short channel effects arise leading to an increasing migration towards NW transistors with gate-all-around configurations to reduce short channel effects such as draininduced barrier lowering (DIBL) and to increase subthreshold current swing through greater electrostatic control of the channel [9]. Advances in top down and bottom up fabrication techniques are leading to reproducible fabrication techniques for NWs with diameters as small as 1 nm [10][11][12]. At these length scales bulk properties do not accurately describe a NW's electronic structure as quantum confinement effects become pronounced, and as well the increase in the surface-tovolume ratio results in the surface strongly influencing electronic properties.…”

“…To explore the interplay between the quantum confinement and surface chemistry for III-V nanowires, electronic structures are studied for gallium arsenide (GaAs) and indium arsenide (InAs) NWs. The primary emphasis is for InAs NWs which due to its small band gap, high electron mobility, and large injection velocity makes this III-V material a promising candidate for the beyondthe-silicon roadmap devices [11].…”