UMHexagonS algorithm based motion estimation architecture for H.264/AVC

Abstract

This paper presents an integer pel variable block motion estimation architecture based on JVT accepted UMHexagonS algorithm for H.264/MPEG-4 Part 10 (AVC) encoder. The proposed pipelined architecture is capable of calculating the required 41 motion vectors of various size blocks supported by H.264/AVC within a 16x16 block in parallel. The architecture can be used for rapid prototyping of motion estimation core using FPGA. The performance analysis shows that the architecture is capable of processing CIF frame sequences in real time considering 5 reference frames within the search range of ±16 at a clock speed of around 30 MHz.

Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding

“…Moreover, the proposed algorithm is tested against two search algorithms implemented by the JM reference encoder, and therefore the results are further divided depending on the reference algorithm used. These reference search algorithms are full search and UMHexagonS search [11]. The results show that the proposed algorithm outperforms both search algorithms.…”

“…The present approach is shown for both cases: 2D and 3D scenarios and the results show a noteworthy time reduction (TR) of up to 99% with only a negligible Rate-Distortion (RD) penalty. Moreover, the proposed algorithm outperforms one of the fastest ME algorithms included in the H.264/AVC JM [10] reference software, namely Unsymmetrical Multi-Hexagon Search (UMHexagonS) [11].…”

Design and analysis of fast search motion estimation architecture for video compression

“…The UMHexagonS search flow diagram is shown in Figure 1. These comparisons are done in four step, consisting of unsymmetrical cross search, uneven multi-hexagon-grid search, extended hexagon-based search, and small diamond search, as shown in Figure 2 [12].…”

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

“…In the literature several works have been proposed concerning the hardware implementation of building blocks of the H.264/AVC codec [6][7][8][9][10][11][12][13][14][15], [18][19][20], [23]. Single-chip coders have been also proposed, as in [4] where a RISC programmable core supports the control tasks while the signal processing functions are all realized by dedicated hardware units.…”

“…The works [19,37] deal with the architecture of a CABAC decoder while in [20] an encoder implementation is investigated. As far as ME is concerned, the adopted solution in [4] is a large systolic array of 256 processing elements implementing a classic Full Search (FS) technique, known to be not efficient in terms of performance vs. complexity trade-off [11][12][13], [23]. Hardware engines based on a systolic array of processing elements for FS ME with variable block sizes have been also proposed in other works, e.g.…”