UML design for dynamically reconfigurable multiprocessor embedded systems

Vidal, Jorgiano; Lamotte, Florent de; Gogniat, Guy; Diguet, Jean-Philippe; Soulard, Philippe

doi:10.1109/date.2010.5456989

Cited by 24 publications

(17 citation statements)

References 11 publications

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“…Another MARTE-based approach is described in [9]. It relies on the MoPCoM project, which defined a co-design methodology based on MDA (Model-Driven Architecture).…”

Section: Related Workmentioning

confidence: 99%

Methodology for designing partially reconfigurable systems using transaction-level modeling

Duhem

Muller

Lorenzini

2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC. Our approach relies on dynamic threads to change the functionality of modules during runtime and on transaction level modeling for all the communications. We introduce a reconfiguration manager to develop and validate scheduling algorithms for hardware tasks management. Moreover, our simulator performs design space exploration in order to find a viable implementation (in terms of reconfigurable zones) for a given application. Our methodology is validated with the modeling of a dynamically reconfigurable video transcoding chain.

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“…Another MARTE-based approach is described in [9]. It relies on the MoPCoM project, which defined a co-design methodology based on MDA (Model-Driven Architecture).…”

Section: Related Workmentioning

confidence: 99%

Methodology for designing partially reconfigurable systems using transaction-level modeling

Duhem

Muller

Lorenzini

2011

Proceedings of the 2011 Conference on Design &Amp; Architectures for Signal &Amp; Image Processing (DASIP)

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“…High-level modeling for reconfigurable systems was proposed in several works. In [7], the authors present a codesign methodology for reconfigurable MPSoC (Multiprocessor SoC), in order to generate automatically reconfigurable embedded systems using the MARTE UML profile. The proposed solution for control modeling is extremely simplistic, based on a UML state machine handling a repeated sequence of configurations for one reconfigurable co-processor.…”

Section: Introductionmentioning

confidence: 99%

Distributed control for reconfigurable FPGA systems: A high-level design approach

Trabelsi

Meftali

Dekeyser

2012

7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-Due to their exponential complexity, designing adaptation control for Reconfigurable Systems-on-Chip (RSoC) is becoming one of the most challenging tasks, resulting in longer design cycles and increased time-to-market. This paper addresses this issue and proposes a novel adaptation control design approach for FPGA-based reconfigurable systems aiming to increase design productivity. This approach combines control distribution and high-level modeling in order to decrease design complexity and enhance design reuse and scalability. Control distribution is based on allocating local control aspects (monitoring, decision and reconfiguration) to distributed controllers, while respecting global system constraints/objectives using a coordinator. High-level modeling makes use of Model-Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard in order to move from high level models to automatic code generation, which significantly simplifies the control design. The proposed design approach is integrated in a model-driven RSoC design flow and allows to model adaptation aspects at different design levels: application, architecture, allocation and deployment, which allows to target a wide range of control requirements. In order to validate our approach, a video processing application was implemented on a reconfigurable system that contained four distributed hardware controllers.

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“…In [14,15] authors use UML and design patterns to explore the design space in a multiprocessor system on programmable chip to capture dynamic properties of both the application and the architecture. Standard UML elements and some well known design patterns are used to model RTR designs.…”

Section: High-level Modelling Of Run-time Reconfigurable Designsmentioning

confidence: 99%

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Uchevler

Svarstad

2018

International Journal of Reconfigurable Computing

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With the increasing design and production costs and long time-to-market for Application Specific Integrated Circuits (ASICs), implementing digital circuits on reconfigurable hardware is becoming a more common practice. A reconfigurable hardware combines the flexibility of the software domain with the high performance of the hardware domain and provides a flexible life cycle management for the product with a lower cost. A complete design and assertion-based verification flow for Run-Time Reconfigurable (RTR) designs using functional programming abstractions of Haskell are proposed in this article, in which partially reconfigurable hardware is used as the implementation platform. The proposed flow includes modelling of RTR designs in high levels of abstraction by using higher-order functions and polymorphism in Haskell, as well as their implementation on partially reconfigurable Field Programmable Gate Arrays (FPGAs). Assertion-based verification (ABV) is used as the verification approach which is integrated in the early stages of the design flow. Assertions can be used to verify specifications of designs in different verification methods such as simulation-based and formal verification. A partitioning algorithm is proposed for clustering the assertion-checker circuits to implement the verification circuits in a limited reconfigurable area in the target FPGA. The proposed flow is evaluated by using example designs on a Zynq FPGA as the hardware/software implementation platform.

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UML design for dynamically reconfigurable multiprocessor embedded systems

Cited by 24 publications

References 11 publications

Methodology for designing partially reconfigurable systems using transaction-level modeling

Methodology for designing partially reconfigurable systems using transaction-level modeling

Distributed control for reconfigurable FPGA systems: A high-level design approach

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

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