Un/DoPack

Tom, Marvin; Leong, David; Lemieux, Guy

doi:10.1145/1233501.1233643

Cited by 21 publications

(1 citation statement)

References 13 publications

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“…H-DPack [Chen et al 2007] is a timing-driven clustering technique which uses physical information to make informed decisions at the clustering stage. iRAC [Singh and Marek-Sadowska 2002] is an example of a technique that uses uniform depopulation with a fixed cluster size and Un/DoPack [Tom et al 2006] uses a nonuniform depopulation technique by varying the cluster size.…”

Section: Clustering Techniquesmentioning

confidence: 99%

Net-length-based routability-driven power-aware clustering

Easwaran

Akoglu

2011

ACM Trans. Reconfigurable Technol. Syst.

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The state-of-the-art power-aware clustering tool, P-T-VPack, achieves energy reduction by localizing nets with high switching activity at the expense of channel width and area. In this study, we employ predicted individual postplacement net length information during clustering and prioritize longer nets. This approach targets the capacitance factor for energy reduction, and prioritizes longer nets for channel width and area reduction. We first introduce a new clustering strategy, W-T-VPack, which replaces the switching activity in P-T-VPack with a net length factor. We obtain a 9.87% energy reduction over T-VPack (3.78% increase over P-T-VPack), while at the same time completely eliminating P-T-VPack's channel width and area overhead. We then introduce W-P-T-VPack, which combines switching activity and net length factors. W-P-T-VPack achieves 14.26% energy reduction (0.31% increase over P-T-VPack), while further improving channel width by up to 12.87% for different cluster sizes. We investigate the energy performance of routability (channel width)-driven clustering algorithms, and show that W-T-VPack consistently outperforms T-RPack and iRAC by at least 11.23% and 9.07%, respectively. We conclude that net-length-based clustering is an effective method to concurrently target energy and channel width.

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Section: Clustering Techniquesmentioning

confidence: 99%

Net-length-based routability-driven power-aware clustering

Easwaran

Akoglu

2011

ACM Trans. Reconfigurable Technol. Syst.

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Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Wang

Trefzer

Bale

et al. 2019

IET Computers & Digital Techniques

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Circuit clustering algorithms fit synthesised circuits into FPGA configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g., power and delay. In this paper, we present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. We address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. Our new approach has been validated using the "Golden 20" MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this paper achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. Key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance. 2 Circuit Clustering in FPGA Design Flow This section provides an overview of the FPGA architecture and state-of-the-art FPGA design flow. In order to implement a complete design onto FPGA, many design objectives have to be considered by automated CAD tools. Fig. 1(a) shows a cluster-based FPGA CAD flow.

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Replace: An incremental placement algorithm for field programmable gate arrays

Leong

Lemieux

2009

2009 International Conference on Field Programmable Logic and Applications

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Recompiling a large circuit after making a few logic changes is a time-consuming process. We present an incremental placement algorithm for FPGAs that is focused on extremely fast runtime for changes which can be localized. It is capable of handling multiple changes across large regions of an FPGA. This is especially useful when used with a floorplan where a modified subcircuit is instantiated several times in the design hierarchy or where several subcircuits are modified. The algorithm is simpler and faster than past approaches because its insertion and legalization steps are based on CPU-efficient shifting steps which do not continuously evaluate the impact of each move on costs. Instead, any lost quality is recovered by a fast, low-temperature anneal at the end. When 35,000 out of 50,000 LUTs are modified, the incremental placement (including fast anneal) is 7 times faster than VPR's "fast placement" from scratch with only 2% quality degradation. The key concepts utilized in the incremental placement algorithm include uses of floor-planning constraints, CPU-efficient CLB shifting, super placement grid and a tuned annealing refinement process.

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Un/DoPack

Cited by 21 publications

References 13 publications

Net-length-based routability-driven power-aware clustering

Net-length-based routability-driven power-aware clustering

Multi‐objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs

Replace: An incremental placement algorithm for field programmable gate arrays

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