Unclamped inductive switching dynamics in lateral and vertical power DMOSFETs

Chinnaswamy, K.; Khandelwal, P.; Trivedi, M.; Shenai, K.

doi:10.1109/ias.1999.801639

Cited by 23 publications

(6 citation statements)

References 10 publications

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“…Nearly 15 years ago, it was shown that high-voltage SiC Schottky diodes when stressed under various circuit switching conditions produced severe failures caused by increased charge generation in defect sites due to high electric fields at increased dv/dt [10]. In silicon power diodes and MOSFETs, our research also showed a direct correlation between field failures and off-state leakage currents [16]. Devices with more defects and higher leakage currents (and soft reverse leakage characteristics) resulted in increased failure rates in the field.…”

Section: The Current Status Of Wide Bandgap Power Switch Reliabilitymentioning

confidence: 64%

Reliability of wide bandgap semiconductor power switching devices

Shenai

2010

Proceedings of the IEEE 2010 National Aerospace &Amp; Electronics Conference

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Section: The Current Status Of Wide Bandgap Power Switch Reliabilitymentioning

confidence: 64%

Reliability of wide bandgap semiconductor power switching devices

Shenai

2010

Proceedings of the IEEE 2010 National Aerospace &Amp; Electronics Conference

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“…This increases the parasitic gate drain capacitance and thus degrades the switching performance of the device [7]- [9]. second, the n+ source-p body and n drift region forms a parasitic BJT which disturbs the normal behavior of the transistor in OFF state [10]- [12]. In order to address the effect of parasitic BJT in the structure, several modi cations have been done in the literature.…”

Section: Introductionmentioning

confidence: 99%

Charge Plasma Based Dual Buried Gates Power MOSFET: Design and Analysis

Nigar,

Alkhammash,

Loan

2024

Preprint

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In this work, we design and simulate a high performance electrostatically doped dual buried gate power MOSFET (EDDBGP-MOS) structure. The novelty of the proposed device is three folds. Firstly, the n + source and P + body regions of the device are realized using induced charge plasma by employing metal electrodes on the silicon film. The device thus reduces the risk of random doping fluctuations and the formation of highly abrupt junctions during fabrication. The high temperature processes involved in defining the doped regions are not required, thus providing low thermal budget. Secondly, the Gaussian hole plasma profile in the p body region allows increase in drift doping concentration from 5x1015/cm3 to 7x1015/cm3 resulting in Ron reduction to almost 24% of its uniformly doped counterpart structure, with only a slight reduction in breakdown voltage of the device. The proposed device thus provides 10% increase in the Baliga’s figure of merit (FOM1 = BV2/Rsp). Further, the linearly graded Gaussian profile at the source side reduces the source coupling with gate. The gate charge together with the reduced specific ON resistance value provides as good as 19% reduction in Baliga’s high frequency figure of merit FOM2 = Rsp.Qsp). As compared to the conventional trench MOSFET structure, the two buried gates in the proposed structure provides low gate drain coupling along with the suppression in parasitic BJT effect. A two-dimensional simulation study of the proposed EDDBGP-MOS device reveals that it outperforms the conventional trench MOSFET device in terms of the performance parameters of power devices, along with the reduced fabrication complexity.

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“…The well-known technique proposed by Bulucea and Rossen [15][16] uses a deep P + region under the substrate, to protect the device from unwanted parasitic turn ON and the initiation of the avalanche process and premature breakdown of the device. Similar such modi cations were also proposed [17]- [21],…”

Section: Introductionmentioning

confidence: 99%

“…These two contacts are shorted together to form the common source. An electron doping of 7x10 15 /cm 3 has been used in the drift region. During ON state, the positive gate voltage creates an inversion layer in the p base region, allowing the electrons from the source plasma region to travel through the inverted channel and drift region to reach the drain end.…”

Section: Introductionmentioning

confidence: 99%

A Charge Plasma Based Dual Buried Gates Power MOSFET with Improved Figure of Merits

Nigar,

Alkhammash,

Loan

2024

Silicon

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In this work, we design and simulate a high performance electrostatically doped dual buried gates power MOSFET (EDDBGP-MOS) structure. The novelty of the proposed device is three folds. Firstly, the n + source and P + body regions of the device are realized using induced charge plasma by employing metal electrodes on the silicon lm. The device thus reduces the risk of random doping uctuations and the formation of highly abrupt junctions during fabrication. The high temperature processes involved in de ning the doped regions are not required, thus providing low thermal budget. Secondly, the Gaussian hole plasma pro le in the p body region allows increase in drift doping concentration from 5x10 15 /cm 3 to 7x10 15 /cm 3 resulting in Ron reduction to almost 24% of its uniformly doped counterpart structure, with only a slight reduction in breakdown voltage of the device. The proposed device thus provides 10% increase in the Baliga's gure of merit (FOM1 = BV 2 /Rsp). Further, the linearly graded Gaussian pro le at the source side reduces the source coupling with gate. The gate charge together with the reduced speci c ON resistance value provides as good as 19% reduction in Baliga's high frequency gure of merit FOM2 = Rsp.Qsp). As compared to the conventional trench MOSFET structure, the two buried gates in the proposed structure provides low gate drain coupling along with the suppression in parasitic BJT effect. A two-dimensional simulation study of the proposed EDDBGP-MOS device reveals that it outperforms the conventional trench MOSFET device in terms of the performance parameters of power devices, along with the reduced fabrication complexity.

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Unclamped inductive switching dynamics in lateral and vertical power DMOSFETs

Cited by 23 publications

References 10 publications

Reliability of wide bandgap semiconductor power switching devices

Reliability of wide bandgap semiconductor power switching devices

Charge Plasma Based Dual Buried Gates Power MOSFET: Design and Analysis

A Charge Plasma Based Dual Buried Gates Power MOSFET with Improved Figure of Merits

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