Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications

Dabhi, Chetan T.; Patil, Ganesh C.

doi:10.1007/s10825-016-0888-0

Cited by 6 publications

(7 citation statements)

References 28 publications

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“…Table 4 illustrates the comparison of proposed H-FGFET with existing floating gate structure. Here the switching ratio of conventional floating gate FET [25], underlap channel SOIQDFG [26], conventional QDFG [26] and JL-TFET with floating gate [27] are compared with horizontal floating gate field effect transistor and it can be observed that proposed H-FGFET offers highest switching ratio and hence the device is suitable for high speed digital circuits, memory designing and sensing applications.…”

Section: Electrical Characteristics Of H-fgfetmentioning

confidence: 99%

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Capacitance modeling, simulation and RF characterization of horizontal floating gate field effect transistor (H-FGFET) for gas sensing application

Babbar,

Garg,

Kabra

2024

Eng. Res. Express

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In this paper, physics-based capacitance model has been developed for horizontal floating gate field effect transistor (H-FGFET). The horizontal design of floating gate (FG) FET allows detection of large gas molecules like nitrogen dioxide (NO2), sulphur dioxide (SO2), hydrogen sulfide (H2S), carbon dioxide (CO2) etc. In order to validate the proposed model, the device has been designed using Sentaurus TCAD simulator and results have been validated with experimental data. Different electrical parameters such as transfer characteristics, switching ratio, output characteristics, threshold voltage, drain induced barrier lowering (DIBL), C-V characteristics, transconductance, output conductance and RF characteristics of the device have been analyzed at room temperature. The simulation result shows that increase in channel length of H-FGFET results in decreased leakage current, improved switching performance, increased gate capacitance and reduced DIBL. The comparative analysis of H-FGFET with previously reported floating gate FET structures reveal that proposed device offers highest switching ratio. The RF characteristics of H-FGFET illustrates that proposed device can operate efficiently as an amplifier for the frequency range of 0.1 GHz to 100 GHz. Further, the proposed device has also been tested for the detection of nitrogen dioxide gas and results reveal that with increase in operating temperature from 30 °C to 180 °C the leakage current of the device increases from 10−13 to 10−9 and OFF current sensitivity of the proposed sensor changes by 82% on changing the work function of sensing layer from 50 meV to 250 meV.

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Section: Electrical Characteristics Of H-fgfetmentioning

confidence: 99%

“…It can be expressed as the ratio of maximum power delivered to load to the input power available from the source. The maximum available gain [29] can be evaluated as: 2.93 × 10 3 Und-SOIQDFG [26] 1.69 × 10 5 Conv-QDFG [26] 0.86 × 10 3 JL-TFET [27] 2.91 ×…”

Section: Rf Characteristics Of H-fgfetmentioning

confidence: 99%

Capacitance modeling, simulation and RF characterization of horizontal floating gate field effect transistor (H-FGFET) for gas sensing application

Babbar,

Garg,

Kabra

2024

Eng. Res. Express

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“…Finally, the I D versus V GS characteristics have been extracted by using the Landau–Khalatnikov equation. The models used in the simulation are Philips unified mobility model, mobility saturation due to high electric field, mobility dependence on transverse electric field, bandgap narrowing, Shockly–Read–Hall and Auger recombination models [ 4, 15, 31, 32 ]. To generate the experimental data reported in [ 33, 34 ], calibration of the mobility models has been carried.…”

Section: Device Structure and Simulation Setupmentioning

confidence: 99%

Negative capacitance δ ‐bulk planar junctionless transistor for low power applications

Patil

2019

Micro & Nano Letters

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The impact of substrate doping on the short-channel effects (SCEs) of bulk-planar junctionless transistor (BPJLT) has been studied. It has been found that increasing substrate doping in bulk region reduces off-state leakage current (I OFF) and the sub-threshold slope (SS) of the device. To further reduce the SCEs of BPJLT heavily doped δ-layer of thickness 10 nm has been added below the channel. Despite the presence of δ-layer in BPJLT reduces SCEs, the SCE, mainly SS, is still limited by the fundamental limit of 60 mV/decade. Therefore, to reduce SS below 60 mV/decade, negative capacitance (NC) δ-BPJLT has been proposed by adding the layer of ferroelectric material at gate stack. It has been found that in comparison with conventional BPJLT and δ-BPJLT, the insertion of ferroelectric layer in NC-δ-BPJLT not only reduces the I OFF and the SS but also improves I ON /I OFF ratio of the device. Thus, embedding heavily doped δ-layer in the bulk region and the ferroelectric layer at the gate stack of BPJLT makes it a promising device for low-power applications.

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“…The materials are investigated to improve the leakage current and retention feature, such as hafnium dioxide (HfO 2 ) as the high k tunnel oxide layer, and germanium (Ge) for the nanocrystal layer. In 2016, the authors in [17] proposed a nanocrystal structure with only 3.3 nm, 5 nm, and 10 nm thicknesses of the tunnel, storage charges, and Interpoly Dielectric (IPD) layers, respectively. With regard to the performance, while the work obtained a large memory window of 3 V, the disadvantages are the considerably high control gate voltage of 12 V and the low writing speed of 0.3 s. On the other hand, in 2018, the work in [18] provided the 0.2 s and 0.04 s of the writing and erasing speeds, respectively.…”

Section: Introductionmentioning

confidence: 99%

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

Cong,

Hoang

2024

Modelling and Simulation in Engineering

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Floating-gate transistor lies at the heart of many aspects of semiconductor applications such as neural networks, analog mixed-signal, neuromorphic computing, and especially in nonvolatile memories. The purpose of this paper was to design a high-performance nanocrystal floating-gate transistor in terms of a large memory window, low power, and extraordinary erasing speeds. Besides, the transistor achieves a thin thickness of the tunnel gate oxide layer. In order to obtain the high-performance design, this work proposed a set of structure parameters for the device such as the tunnel oxide layer thickness, Interpoly Dielectric (IPD), dot dimension, and dot spacing. Besides, this work was successful in the virtual fabrication process and methodology to fabricate and characterize the 65 nm nanocrystal floating-gate transistor. Regarding the results, while the fabrication process solves the limitation of the tunnel oxide layer thickness with the small value of 6 nm, the performance of the transistor has been significantly improved, such as 2.8 V of the memory window with the supply voltage of ±6 V at the control gate. In addition, the operation speeds are compatible, especially the rapid erasing speeds of 2.03 μs, 28.6 ns, and 1.6 ns when the low control gate voltages are ±9 V, ±12 V, and ±15 V, respectively.

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Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications

Cited by 6 publications

References 28 publications

Capacitance modeling, simulation and RF characterization of horizontal floating gate field effect transistor (H-FGFET) for gas sensing application

Capacitance modeling, simulation and RF characterization of horizontal floating gate field effect transistor (H-FGFET) for gas sensing application

Negative capacitance δ ‐bulk planar junctionless transistor for low power applications

A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor

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