Understanding the forbidden pitch phenomenon and assist feature placement

Shi, Xuelong; Hsu, Stephen; Chen, J. Fung; Hsu, Chungwei Michael; Socha, Robert; Dusa, Mircea V.

doi:10.1117/12.473427

Cited by 31 publications

(20 citation statements)

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“…Pileggi et al proposed a scheme called via-programmable gate array (VPGA) (Figs. 8,9,10), where, the metal lines have regular runs and the personalization for logic is controlled by patterning the vias that connect one metal layer with another [13,14]. We investigated the viability of this technique as a potential 45 nm technology solution by running aerial imaging simulation.…”

Section: Resultsmentioning

confidence: 99%

“…One other effect is the variation in dimensions of identical features depending on whether those features are densely or sparsely packed. This effect is mitigated by adding assist features of lesser resolution than that of the imaging system near an isolated feature, thus changing the shape of the light pattern to match the densely packed features [8,9].…”

Section: Diffraction Theorymentioning

confidence: 99%

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Forbidden pitches in sub-wavelength lithography and their implications on design

Kundu

Sreedhar

Sanyal

2007

J Computer-Aided Mater Des

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Moore's Law has been the most important benchmark for microelectronics development over the past four decades. It has been interpreted to mean that critical dimensions (CD) of a design must shrink geometrically over time. The chip-level integration of devices has been possible through concurrent improvement in lithographic resolution. The lithographic resolution was primarily improved by moving deeper into ultraviolet spectrum of light. However, the wavelength of the optical source used for lithography has not improved for nearly a decade. This has lead to the development of sub-wavelength lithography. The diffraction effects of sub-wavelength lithography were offset by optical proximity correction (OPC), phase shift masking (PSM) and impending move to immersion lithography. Unfortunately, one time benefits from each of these resolution enhancement techniques (RET) have nearly exhausted. In this paper, we explore one important diffraction aspect of sub-wavelength lithography viz. the forbidden pitch phenomenon and its implication on future designs. We studied Forbidden pitches in context of 65 and 45 nm technologies using aerial imaging simulation. Aerial imaging simulation is computationally expensive and is not possible to perform on entire layout structures. Based on results from our simulations on selected patterns, we observe that in absence of any other resolution enhancement technique, many of the current layout patterns will be disallowed in 45 nm technology. Such restrictions significantly mitigate the benefit of migration to 45 nm technology in terms of area, power and performance of a design. We further show that even structured gate array based designs are not immune to this problem.

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Section: Resultsmentioning

confidence: 99%

Section: Diffraction Theorymentioning

confidence: 99%

Forbidden pitches in sub-wavelength lithography and their implications on design

Kundu

Sreedhar

Sanyal

2007

J Computer-Aided Mater Des

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“…Off axis illumination (OAI) technique is applied as OAI amplifies certain pitch at the cost of others. This phenomena is called "Forbidden" pitch [13,14]. In order to overcome this OAI limitation, sub-resolution assist feature (SRAF) [5] is accounted in our optimization.…”

Section: Post Lithography Aerial Image Simulation Modelmentioning

confidence: 99%

Design rule optimization of regular layout for leakage reduction in nanoscale design

Subramaniam

Singhal

Wang

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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-The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ~10% and marginal impact on circuit speed and active power.

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“…Socha et al [18] observe that under more aggressive illumination schemes such as annular and quasar illuminations, some optical phenomena become more prominent, most notably the forbidden-pitch phenomenon. Shi et al [17] give a theoretical analysis of pattern distortion in forbidden pitches due to the destructive light-field interference. Although SRAFs are an effective method to collect high-order diffraction on the entrance pupil plane of a projection lens [15], Shi et al report that incorrect SRAF placements around a given main feature can actually degrade the process latitude of that feature.…”

Section: A Ret and Layout Impactmentioning

confidence: 99%

“…In this section, we summarize the criteria for SRAF insertion and forbiddenpitch extraction considering a worst defocus model. Our SRAF insertion rule is initially generated based on the theoretical background given in [17]. Positioning of SRAFs is then adjusted based on OPC results.…”

Section: B Sraf Rule and Forbidden-pitch Extractionmentioning

confidence: 99%

Enhanced Design Flow and Optimizations for Multiproject Wafers

Kahng

Măndoiu

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Subresolution assist feature (SRAF) and etchdummy insertion techniques have been absolutely essential for process window enhancement and CD control in photo and etch processes. However, as focus levels change during lithography manufacturing, CDs at a given "legal" pitch can fail to achieve manufacturing tolerances. Placed standard-cell layouts may not have the ideal whitespace distribution to allow for an optimal assist-feature insertion. This paper first describes a novel dynamic programming-based technique for Assist-Feature Correctness (AFCorr) in detailed placement of standard-cell designs. At the same time, etch-dummy features are used in the mask data preparation flow to reduce CD skew between resist and etch processes and to improve the printability of layouts. However, etch-dummy rules conflict with the SRAF insertion because each of the two techniques requires specific design rules. We further present a novel SRAF-aware etch-dummy insertion method (SAEDM) which optimizes the etch-dummy insertion to make the layout more conducive to the assist-feature insertion after the etch-dummy features have been inserted. Since placement of cells can create forbidden-pitch violations of resist process and can increase etch skew, the placer must also generate etchdummy-correct placement. This can be solved by Etch-dummy Correctness (EtchCorr), which is an intelligent whitespace management for etch-dummy-corrected placement, an extension of the AFCorr methodology. These methods for enhanced resist and etch CD control are validated on industrial test cases with respect to wafer printability, database complexity, and device performance. For benchmark designs, we validate the four methodologies: 1) AFCorr; 2) SAEDM; 3) AFCorr + SAEDM; and 4) AFCorr + EtchCorr + SAEDM. The AFCorr placement perturbation achieves a significant reduction in forbidden pitches between polysilicon shapes. Using 1) flow, forbidden-pitch count of photo process is reduced by 76%-100% for 130 nm and by 87%-100% for 90 nm. Our novel Corr design-perturbation technique, which combines the AFCorr and EtchCorr methods, facilitates additional SRAF and etch-dummy insertions and, thus, reduces the CD skew between the photo and etch processes. After Corr with SAEDM, edge placement error (EPE) count is also reduced by 91%-100% in the resist CD and by 72%-98% in the etch CD. Our methods provide a substantial improvement in CD control with negligible timing, area, and CPU overhead. The advantages

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Understanding the forbidden pitch phenomenon and assist feature placement

Cited by 31 publications

References 0 publications

Forbidden pitches in sub-wavelength lithography and their implications on design

Forbidden pitches in sub-wavelength lithography and their implications on design

Design rule optimization of regular layout for leakage reduction in nanoscale design

Enhanced Design Flow and Optimizations for Multiproject Wafers

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