2018 IEEE 68th Electronic Components and Technology Conference (ECTC) 2018
DOI: 10.1109/ectc.2018.00117
|View full text |Cite
|
Sign up to set email alerts
|

Understanding the Impact of PCB Changes in the Latest Published JEDEC Board Level Drop Test Method

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
0
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
4
1

Relationship

1
4

Authors

Journals

citations
Cited by 8 publications
(2 citation statements)
references
References 9 publications
0
0
0
Order By: Relevance
“…Similar results are observed by Thukral et al [31] during board level drop testing [30]. In addition, the peak-peak displacement of the JESD-B111A is lower than the JESD-B111 type board design.…”
Section: Test Board Designssupporting
confidence: 88%
“…Similar results are observed by Thukral et al [31] during board level drop testing [30]. In addition, the peak-peak displacement of the JESD-B111A is lower than the JESD-B111 type board design.…”
Section: Test Board Designssupporting
confidence: 88%
“…Generally, the components located in the middle of this test board (referred as Group A) receive the maximum amount of stress as compared to the remaining devices under test (referred as Group B) [2][10]. It is also established in the temperature coupled vibration test reliability assessment.No failures are observed in Group B & C after 2051 minutes.…”
mentioning
confidence: 99%