Understanding the impact of transistor-level BTI variability

Fang, Jianxin; Sapatnekar, Sachin S.

doi:10.1109/irps.2012.6241887

Cited by 13 publications

(7 citation statements)

References 8 publications

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“…By inspecting the atomistic BTI-related literature, it is evident that it lacks a comprehensive atomistic BTI modeling flow for subsystem-wide reliability analysis. Previous works have been mostly focusing either on simple CMOS logic gates [3,13] and SRAM cells [5,10,11,14] or on larger netlists of repetitive logic subblocks with reduced functional complexity [4,15,16]. Thus, we observe a limited usability of SotA atomistic BTI models for more complex netlists and realistic CPU modules.…”

Section: Related Work and Motivationmentioning

confidence: 93%

“…Minority carriers are trapped and emitted from these sites, leading to V th fluctuations. A variety of related imple- [3,13] CMOS Logic Gates 6 Gates [10,14] 6T SRAM cell 6 Gates [5,11] subset of SRAM 244 Gates [15] Benchmark Circuits 68,000 RTL/ALU [4] Array Multiplier 229,376 RTL/ALU [16] Logic Subblocks * N/A * * RTL/ALU Ours CPU module 1830 Subsystem * Adders, multipliers, mux-demux and shifter blocks * * Not explicitly reported mentations exist, modeling BTI either over arbitrary circuit lifetime intervals [10] or in a transient way [11]. However, atomistic BTI modeling comes with increased processing overheads.…”

Section: Related Work and Motivationmentioning

confidence: 99%

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Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Stamoulis

Rodopoulos²,

Meyer

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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In this paper, we propose EDA methodologies for efficient, datapath-wide reliability analysis under Bias Temperature Instability (BTI). The proposed EDA flow combines the efficiency of atomistic, pseudo-transient BTI modeling with the accuracy of commercial Static Timing Analysis (STA) tools. In order to reduce the transistor inventory that needs to be tracked by the STA solver, we develop a thresholdpruning methodology to identify the variation-critical part of a design. That way, we accelerate variation-aware STA iterations, with a maximum speedup of 6.82x achieved for representative benchmark circuits. We substantiate the efficiency of the proposed framework for realistic designs. For a CPU datapath, our threshold-pruning technique outperforms built-in pruning commands of the STA solver by 16.87% in terms of runtime improvement. We demonstrate the impact of BTI after three years of operation, with clock frequency degradation up to 24% and functional yield reduction below 90% for higher frequencies.

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Section: Related Work and Motivationmentioning

confidence: 93%

Section: Related Work and Motivationmentioning

confidence: 99%

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Stamoulis

Rodopoulos²,

Meyer

et al. 2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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“…The lack of correlation between multiple trapped charges justifies simpler models accounting for BTI degradation of transistors in circuit simulations [7]- [9], where the change in V T due to the trapping of an extra charge is modeled by the addition of V T ,1 , randomly selected from an exponential distribution. However, the values reported in Fig.…”

Section: Correlation Effects In V T Distributionmentioning

confidence: 99%

“…The interplay between statistical variability and the degradation phenomena in transistors implies that their performance-and reliability-related parameters must be evaluated as stochastic variables [3]- [5]. It is now experimentally established that the capture and emission dynamics of oxide traps underlie both random telegraph noise (RTN) and bias-temperature instability (BTI) [6], thus motivating the inclusion of these effects in statistical simulations of contemporary devices and circuits [2], [7]- [9]. However, all previous statistical simulation studies assume that trapped charges act as uncorrelated sources of noise, and that the number of trapped charges remains Poissonian at all times.…”

Section: Introductionmentioning

confidence: 99%

Statistical Interactions of Multiple Oxide Traps Under BTI Stress of Nanoscale MOSFETs

Markov

Amoroso

Gerrer

et al. 2013

IEEE Electron Device Lett.

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We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for timedependent variability in circuits. Index Terms-Bias and temperature instability (BTI), complimentary metal-oxide-semiconductor (CMOS), random telegraph noise (RTN), reliability, variability.

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“…The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in the channel, to the point where they gain enough energy and momentum to cause damage, degrading mobilities and threshold voltages.…”

Section: Introductionmentioning

confidence: 99%

What happens when circuits grow old: Aging issues in CMOS design

Sapatnekar¹

2013

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

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As CMOS technologies have shrunk to tens of nanometers, aging problems have emerged as a major challenge. There has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors, but much less work on propagating these models to higher levels of abstraction to analyze and optimize the reliability of larger circuits. This talk will provide an introduction to various circuit aging mechanisms and will then discuss research that develops computer-aided design techniques for estimating and enhancing the reliability of large digital circuits, examining solutions that could practically be applied to analyze or improve the lifetime of a design while maintaining consistency to accurate device-level models and the associated physics.CIRCUIT-LEVEL ANALYSIS OF AGING Aging effects are described by the classical bathtub curve: after a steep initial failure rate, the failures level off for a while before rising again, resulting in a bathtub-like shape for the number of failures as a function of time. Aging is strongly sensitivity to process parameter variations, as well as to onchip temperature and supply voltage level changes. Here, we overview analysis methods for prominent aging mechanisms, based on both conventional and newer physical models. Bias temperature instability (BTI) is a device aging phenomenon that causes threshold voltage shifts over long periods of time in the presence of voltage stress at the gate, eventually causing the circuit to fail to meet its specifications. A PMOS transistor in an inverter experiences negative BTI stress when its gate node is at logic 0, and the resulting increase in the threshold voltage is partially reversed when the voltage stress is removed (i.e., a logic 1 is applied). A similar phenomenon of positive BTI affects the threshold voltage of NMOS devices when they are stressed, and relaxes the degradation on the removal of stress. The magnitude of degradation depends on the ratio of the stressed time to unstressed time, i.e., the signal probability (SP) of the gate input. There are two widely-used theories for BTI. The reaction-diffusion (R-D) model [1,2] explains the degradation due to the accumulation of positive charges as Si-H bonds at the interface are broken and hydrogen diffuses away; the removal of this stress allows partial restoration of these bonds. The charge-trapping (CT) model [3] provides an alternative explanation, where defects in gate dielectrics can capture charged carriers, causing the threshold voltage to degrade. Neither theory fully explains experimental observations, and it has been posited that R-D and CT mechanisms coexist. The CT model predicts high variability in small devices, making variability a major factor for memories. For logic circuits, however, large transistors and averaging effects on critical paths significantly mitigate variability [4]. Hot carrier injection (HCI) in MOSFETs is caused by the acceleration of carriers (electrons/holes) under lateral electric fields in th...

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Understanding the impact of transistor-level BTI variability

Cited by 13 publications

References 8 publications

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models

Statistical Interactions of Multiple Oxide Traps Under BTI Stress of Nanoscale MOSFETs

What happens when circuits grow old: Aging issues in CMOS design

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