Ferroelectric devices have gained attention in recent years as a potential solution for ultra-low power computing due to their ability to act as memory units and synaptic weights in brain-inspired architectures. One way to study the behavior of these devices under different conditions, particularly the influence of material composition and charge trapping on ferroelectric switching, is through impedance spectroscopy. However, the parasitic impedance of the metal lines that contact the electrodes of the device can affect the measured response and interpretation of the results. In this study, we examined the frequency response of ferroelectric tunnel junctions (FTJs) with a metal-dielectric-ferroelectric-metal (MDFM) stack at various voltages, starting from the analysis of single layer capacitors (MFM and MDM) to better interpret FTJ's results. To accurately assess the intrinsic response of the device, we developed a method that estimates and removes the parasitic access impedance contribution, which was validated by means of physics-based simulations. This method allows quantifying the intrinsic device-level variability of FTJs and, for the first time, to investigate the relation between the thickness of the dielectric layer, the equivalent phase composition of the ferroelectric material, and the magnitude of the peak in the frequency response, often assumed to be related to charge trapping only.