Understanding the Role of CdTe in Polycrystalline CdSe_xTe_1–x/CdTe‐Graded Bilayer Photovoltaic Devices

Abstract

Grading of bandgap by alloying CdTe with selenium to form a CdSe x Te1–x /CdTe‐graded bilayer device has led to a device efficiency over 19%. A CdSe x Te1–x absorber would increase the short‐circuit current due to its lower bandgap but at the expense of open‐circuit voltage. It has been demonstrated that adding a CdTe layer at the back of such a CdSe x Te1–x film reduces the voltage deficit caused by the lower bandgap of absorber from selenium alloying while maintaining the higher short‐circuit current. This leads to a photovoltaic device that draws advantage from both materials with an efficiency greater than either of them. Herein, a detailed account using device data, ultraviolet photoelectron spectroscopy, electron microscopy, and first‐principles density functional theory modeling is provided, which shows that CdTe acts as an electron reflector for CdSe x Te1–x .

Investigation of Sub‐Bandgap Emission and Unexpected n‐Type Behavior in Undoped Polycrystalline CdSexTe1‐x

“…[55] This could also be a reason CST-only devices (including graded CdSe 0.4 Te 0.6 /CdSe 0.2 Te 0.8 devices) do not typically perform as well as graded CST/CdTe devices. [56] In addition to the electron reflector role Shah et al demonstrated CdTe plays at the back, [56] recombination may be lower at the back of CST/CdTe devices due to, at least partially, the reduced electron density there. Knowing that CST (no intentional doping) can be strongly n-type and accounting for this may open avenues to make highly doped ntype devices, particularly since the CST measured here showed an electron density of 10 16 -10 17 cm −3 (assuming an electron mobility of 100 cm 2 Vs −1 ).…”

Impact of CdSeTe and CdSe film deposition parameter on the properties of CdSeTe/CdTe absorber structure for solar cell applications

“…In order to overcome the factors limiting the performance of the solar cells with Cd(Se,Te) interlayer, the studies were concentrated on the optimization of fabrication conditions such as their thickness, the effect of Cu doping on them, minority carrier lifetime, defect structure, CdCl 2 treatment, etc [9][10][11][12][13][14][15]. Among the existing conditions of fabrication, substrate temperature (ST) is an important parameter because it directly affects phase formation, grain size and conductivity of the CdSe and/or CdTe films as well as the quality of the interface at the CdSe/CdTe or Cd(Se,Te)/CdTe stacks [16][17][18][19].…”

Front interface defect signature and benefits of CdSeTe thickness and band gap in CdSeTe/CdTe graded solar cell

“…MZO and CdSe x Te 1-x (CdSeTe) improve the carrier collection at short and long wavelength, respectively [6] maximizing the short-circuit current density (J SC ), currently exceeding 30 mA/cm 2 [9]. The graded absorber bilayer, CdSe x Te 1-x /CdTe, is necessary to maintain simultaneously high values of open-circuit voltage and short-circuit current [10]. Despite this improvements the open circuit voltage remain below 900 mV far from the detailed-balance value of 1.156 V [11].…”