Unfaithful Glitch Propagation in Existing Binary Circuit Models

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Najvirt

et al. 2018

Self Cite

Accurate delay models are important for static and dynamic timing analysis of digital circuits, and mandatory for formal verification. However, Függer et al. [IEEE TC 2016] proved that pure and inertial delays, which are employed for dynamic timing analysis in state-of-the-art tools like ModelSim, NC-Sim and VCS, do not yield faithful digital circuit models. Involution delays, which are based on delay functions that are mathematical involutions depending on the previous-output-toinput time offset, were introduced by Függer et al. [DATE'15] as a faithful alternative (that can easily be used with existing tools). Although involution delays were shown to predict real signal traces reasonably accurately, any model with a deterministic delay function is naturally limited in its modeling power.In this paper, we thus extend the involution model, by adding non-deterministic delay variations (random or even adversarial), and prove analytically that faithfulness is not impaired by this generalization. Albeit the amount of non-determinism must be considerably restricted to ensure this property, the result is surprising: the involution model differs from non-faithful models mainly in handling fast glitch trains, where small delay shifts have large effects. This originally suggested that adding even small variations should break the faithfulness of the model, which turned out not to be the case. Moreover, the results of our simulations also confirm that this generalized involution model has larger modeling power and, hence, applicability.

Section: Faithfulness Of Involution Channels With Adversarial Choicementioning

confidence: 57%

Section: Faithfulness Of Involution Channels With Adversarial Choicementioning

confidence: 84%

Section: Faithfulness Of Involution Channels With Adversarial Choicementioning

confidence: 99%

Section: Signalsmentioning

confidence: 99%

See 2 more Smart Citations

A faithful binary circuit model with adversarial noise

Függer

2018 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

Najvirt

et al. 2018

Self Cite

“…2: Principle functionality of a single-history delay model. Based on the input-to-previous output transition time T , the delay δ(T ) is determined [6].…”

Section: Introductionmentioning

confidence: 99%

Transistor-Level Analysis of Dynamic Delay Models

2019 25th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

Függer

Nowak

et al. 2019

Self Cite

Delay estimation is a crucial task in digital circuit design as it provides the possibility to assure the desired functionality, but also prevents undesired behavior very early. For this purpose elaborate delay models like the Degradation Delay Model (DDM) and the Involution Delay Model (IDM) have been proposed in the past, which facilitate accurate dynamic timing analysis: Both use delay functions that determine the delay of the current input transition based on the time difference T to the previous output one. Currently, however, extensive analog simulations are necessary to determine the (parameters of the) delay function, which is a very time-consuming and cumbersome task and thus limits the applicability of these models. In this paper, we therefore thoroughly investigate the characterization procedures of a CMOS inverter on the transistor level in order to derive analytical expressions for the delay functions. Based on reasonably simple transistor models we identify three operation regions, each described by a different estimation function. Using simulations with two independent technologies, we show that our predictions are not only accurate but also reasonably robust w.r.t. variations. Our results furthermore indicate that the exponential fitting proposed for DDM is actually only partially valid, while our analytic approach can be applied on the whole range. Even the more complex IDM is predicted reasonably accurate.

Gain and Pain of a Reliable Delay Model

2021 24th Euromicro Conference on Digital System Design (DSD)

2021

In this paper we evaluate a promising delay estimation method, the Involution Delay Model. We apply it to three simple circuits (a combinatorial loop, an SR latch and an adder), interpret the delivered results and determine realistic overhead estimations. Comparisons to analog SPICE simulations reveal fine-grained behavioral coverage, whereat the commonly used digital inertial delay model shows severe shortcomings. Overall, the Involution Delay Model is able to identify a wide range of malicious behavior and is thus a viable upgrade to available delay models in modern digital timing simulation tools.