Unified approach for Performance Evaluation and Debug of System on Chip at early design phase

Gupta, Nishit; Alag, Sunil

doi:10.1109/ic3.2015.7346716

2015 Eighth International Conference on Contemporary Computing (IC3) 2015

DOI: 10.1109/ic3.2015.7346716

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Unified approach for Performance Evaluation and Debug of System on Chip at early design phase

Nishit Gupta

Sunil Alag

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2016

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Cited by 2 publications

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Novel approach for cache memory simulation at approximately-timed TLM abstraction level for SMP system

Gupta

Alag

2016

2016 5th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO)

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Unified approach for Performance Evaluation and Debug of System on Chip at early design phase

Cited by 2 publications

References 11 publications

Novel approach for cache memory simulation at approximately-timed TLM abstraction level for SMP system

Novel approach for cache memory simulation at approximately-timed TLM abstraction level for SMP system

NTRP: Novel approach for DUT testing based on nonintrusive timing randomization probes using SystemC verification library

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