Unified OpenCL Integration Methodology for FPGA Designs

Abstract

OpenCL is a widely adopted open standard for general purpose programming of diverse heterogeneous parallel platforms that can harness various device types such as CPUs, DSPs, GPUs, FPGAs and hardware accelerators. It is an extensive and explicit low level API serving well as a platform portability layer. However, using OpenCL for diverse heterogeneous programming in multi-vendor platforms is not practical due to device vendors each providing their own OpenCL implementations which do not interoperate efficiently, leading to inefficient execution coordination and collaborative execution between various device types from different vendors.To this end, this paper proposes a vendor-independent open source method for integration of custom FPGA components to a common OpenCL platform. The method relies on a streamlined memory-mapped hardware control interface implemented by the integrated components. The required OpenCL driver integration is then automatically provided, enabling easy inclusion of different types of FPGA accelerators to the control of a single OpenCL runtime.The ease of integration and portability is demonstrated by integrating two hardware devices in two different FPGA devices. The resource overhead of the hardware interface is shown to be negligible and the clock frequency overheads small enough to not pose efficiency challenges.

Cross-vendor programming abstraction for diverse heterogeneous platforms

“…For example, communication and synchronization through a shared memory hierarchy between different devices should be taken into account when defining the hardware control interface. Examples of such hardware interfaces are HSA (HSA TM Foundation, 2018) and AlmaIF (Leppänen et al, 2021), the latter was used in the evaluation of this work. In the longer term, we believe efficient interoperability between heterogeneous devices still requires further interface specification work, similar to what was done in HSA, in order to probe for an efficient peer-to-peer communication and synchronization means without resorting to device-pair-specific intelligence in the driver layer.…”

“…The first device simply moved the stream of data to on-chip memory, while the second device processed the data further to produce a classification result. The devices implement the hardware interface by Leppänen et al (2021) to allow them to be connected to the OpenCL implementation PoCL. The common interface also enabled them to communicate and share data directly with each other on-chip.…”

“…This makes the first device to be very similar to typical stream-to-memorymapped DMA components. The main difference is the hardware interface (Leppänen et al, 2021) it implements so that it can be connected to PoCL and controlled just like any OpenCL device by enqueuing built-in kernels. The device's hardware description was created with Vitis HLS tools starting from C language input, which demonstrates that the built-in kernel implementations can be generated with vendor tools, but used as part of vendorindependent abstraction.…”