Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips

Abstract

On-chip wireless interconnects have been demonstrated to improve the performance and energy consumption of data communication in Network-on-Chips (NoCs). However, the wireless interfaces (WIs) can be defective, rendering these broken links severely affect the performance. This makes manufacturing test of the WIs critical. While analog testing of the transceivers is possible, such methodologies are impractical in a Wireless NoC (WiNoC) due to large overheads. In addition to testing, security is another prominent challenge in WiNoCs, as the security breach can happen due to embedded hardware Trojans or through external attacker exploiting the wireless medium. The typical security measures used in general wireless networks are not practical in a WiNoC due to unique network architectures and performance requirements of such a system. However, both testing and security defense can potentially leverage a basic monitoring framework which, can detect malfunctions or anomalies. Based on this idea, we propose a unified architecture for testing and attack detection and protection of on-chip wireless interconnects. We adopt a Built-In-Self Test (BIST) methodology to enable online monitoring of the wireless interconnects which can also be reused for monitoring the security threats. We focus on manufacturing defects of the WIs for testing and persistent jamming attack for the security measures, as this kind of attack is most likely on wireless communication systems. The BIST methodology is capable of detecting faults in the wireless links with a low aliasing probability of 2.32× 10 −10 . Additionally, the proposed unified architecture is able to detect the persistent jamming with an accuracy of 99.87% and suffer < 3% communication bandwidth degradation even in the presence of attacks from either internal or external sources.

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

“…Machine learning (ML)-based techniques [27], [57] seem promising as the stateof-the-art ML classifiers are utilized to detect HTs effectively. A built-in-self test based methodology is presented in [58] V. CONCLUSION In this work, we surveyed the state-of-the-art works that focus on the HT design and their implementation on various hardware platforms. HTs can do severe damage to the cyberphysical systems, as we observe from the discussion.…”

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

“…To protect the chip against possible external eavesdroppers, the authors used a simple data scrambling approach in the form of XORing the flits with the same (periodically changing) key. For internal eavesdropping attacks, though, they have equipped the input port with a low [108], [109].…”

“…Violating WIs will be shut down by the power management unit to turn off that malicious WI. However, this mechanism would fail to protect the system in case of broadcast packets [108], [109].…”

“…In [111] the authors have exploited a similar technique to the one utilized in [108], [109] to counter jamming attacks on a different architecture called Network-in-Package (NiP). More than one multi-core chip are considered to communicate wirelessly in this architecture, while cores in each chip are connected using a wired mesh.…”

What Can a Remote Access Hardware Trojan do to a Network-on-Chip?

“…However, with increasing number of security zones, it is hard to reduce inter-zone traffic and requires complicated scheduling policy. Recent works such as [9], [10], [11] propose detection of HTs in NOCs, but are limited to detecting HTs leading to eavesdropping and DoS attacks. In [12], authors proposed Non-Interference Based adaptive (NIBR) Routing to secure NoCs from side channel and DoS attacks.…”