Unified-TP: A Unified TLB and Page Table Cache Structure for Efficient Address Translation

Ma, Zhulin; Tan, Yujuan; Jiang, Hong; Yan, Zhongjiang; Liu, Duo; Chen, Xianzhang; Zhuge, Qingfeng; Sha, Edwin Hsing-Mean; Wang, Cheng-Liang

doi:10.1109/iccd50377.2020.00052

Cited by 3 publications

(2 citation statements)

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“…The allocators in [17], [18] are based on the legacy buddy algorithm that has size and alignment restrictions, whereas our design supports unaligned ranges. In [19], the unified TLB and the page-table cache are presented. In [19], pagetable cache entries are stored with TLB entries to reduce TLB misses.…”

Section: Iommu and Memory Allocationmentioning

confidence: 99%

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Page-Size Aware Buddy Allocator With Unaligned Range Supports for TLB Coalescing

Duong,

Hur

2023

IEEE Access

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It is well known that the traditional page-based address translation scheme has limited translation look-aside buffer (TLB) reach and page-table walk overheads. A TLB coalescing scheme reduces these problems by representing an address range in a TLB entry. However, the conventional physical memory allocator has the power-of-2 block size and the address alignment restrictions. As a result, it is difficult to utilize diverse contiguities in memory and exploit the capability of TLB coalescing. To alleviate these issues, in the context of eager paging for I/O devices, we propose the flexible physical memory allocator that can represent unaligned ranges within the page sizes defined in the machine architecture. Combined with TLB coalescing, the presented scheme can efficiently utilize the contiguity in memory and reduce page-table walks. Considering the binary buddy allocator as a baseline, we present an algorithm, a design, analyses, a case study, an implementation, and evaluations. The experimental results indicate the presented scheme can improve memory utilization, TLB performance, and system performance.

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Section: Iommu and Memory Allocationmentioning

confidence: 99%

“…In [19], the unified TLB and the page-table cache are presented. In [19], pagetable cache entries are stored with TLB entries to reduce TLB misses. In [20], page-table walk requests are rescheduled to reduce GPU stalls.…”

Section: Iommu and Memory Allocationmentioning

confidence: 99%