Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch

Tu, Charng-Gan; Huang, Yuexiang; Cheng, Chih Ming; Tsai, Chung-En; Chen, Jyun-Yan; Ye, Hung-Yu; Lu, Fung Jou; Liu, C. W.

doi:10.1109/ted.2021.3050430

Cited by 16 publications

(9 citation statements)

References 23 publications

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“…The Ge content of 95% in GeSi channels is larger than 85% to ensure the electrons populated in the high mobility L 4 valleys 13 . In previous work 20 , 21 , the nanosheets have non-uniform electron distribution across the cross sections, where electron wavefunction is dense at both ends. This causes the degradation of I ON per footprint as compared with the nanowires.…”

Section: Resultsmentioning

confidence: 84%

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

Chen,

Liu,

Lin

et al. 2023

Commun Eng

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Horizontal gate-all-around field effect transistors (GAAFETs) are used to replace FinFETs due to their good electrostatics and short channel control. Highly stacked nanowire channels are widely believed to enhance drive current of these devices and improve overall transistor density due to their small footprint. Here we demonstrate the fabrication and characterization of nanowire FETs with stacked 16 Ge0.95Si0.05 nanowires and stacked 12 Ge0.95Si0.05 nanowires without parasitic channels. The device has the high on current (ION) of 190 μA per stack (9400 μA/μm per channel footprint) at overdrive voltage (VOV) = drain-source voltage (VDS) = 0.5 V and the high maximum transconductance (Gm,max) of 490μS (24000μS/μm) at VDS = 0.5 V among reported Si/Ge/GeSi 3D nFETs. Note that the transistor performance can be evaluated by the delay, which is depicted as CV/I. If the transistor ION is improved, the delay of standard cell can be reduced, leading to faster operation of the circuit. The subthreshold slope reduction and ION/IOFF improvement are achieved by the parasitic channel removal. In technology computer aided design (TCAD) simulation, the wrap around contacts are useful to reduce the current difference between the channels. With the proper design of transistor height, the gate delay can be also improved.

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Section: Resultsmentioning

confidence: 84%

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

Chen,

Liu,

Lin

et al. 2023

Commun Eng

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“…Up to now, there are only three groups that have demonstrated the presence of vertically stacked Ge (Sn) GAA NW FETs owing to the cutting-edge Ge (Sn) CVD growth technology (Table 3). After carefully considering the band alignment and strain engineering, M. Liu et al [192] designed the GeSn/Ge heterostructure-based high-performance vertically stacked GAA NW FETs with traditional Si CMOS processing technology. The main growth processes are as follows: (I) growth of the intrinsic Ge layer on Si (100) substrate in an RPCVD reactor; (II) 200 nm thick p-type doped Ge layer growth (boron doping concentration: 2.5 × 10 19 cm −3 ); (III) 150 nm thick slightly p-type doped Ge layer growth, which is used for channel length definition; (IV) 60 nm thick GeSn layer with 8% Sn incorporation.…”

Section: Epitaxy Of Gesi and Ge For Channel Regionmentioning

confidence: 99%

“…It should be noted that fabrication processes should be implemented at the low thermal budget, thus maintaining the structural stability for GeSn. [192]. Reprinted with permission from ref.…”

Section: Epitaxy Of Gesi and Ge For Channel Regionmentioning

confidence: 99%

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CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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“…15 The different thicknesses of Al 2 O 3 and HfO 2 were also investigated in this work because the amount of Ge in HfO 2 has an effect on ferroelectricity. Recently, stacked gate-all-around fieldeffect transistors (GAAFETs) including multiple-channel structures of nanosheets [16][17][18][19] and nanowires (NWs) [20][21][22][23] have been extensively considered to boost the driving current and overcome the issue of short-channel effects to continue Moore's law to future technology nodes, owing to their excellent electrostatic characteristics. Ge diamond-shaped NW with (111) channel surfaces along 〈110〉 direction shows excellent device performance with greatest electrostatic control and high I on /I off .…”

mentioning

confidence: 99%

Self-Induced Ge-Doped HfO₂ Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O₃ Treatment with GeO₂ as Interfacial Layer

Lin,

Huang,

Lin

et al. 2024

ECS J. Solid State Sci. Technol.

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This study reports a self-induced ferroelectric Ge-doped HfO2 (Ge:HfO2) thin film through interface reactions. In the first experiment, three treatments for forming interfacial layer (IL) were discussed through TiN/2-nm-thick Al2O3/2-nm-thick Ge:HfO2/GeO2/Ge metal-ferroelectric-insulator-semiconductor capacitors. The remnant polarization (Pr), leakage current, and interface trap density (Dit) were compared to select the most appropriate IL treatment. The results show that the in-situ ozone treatment under the standard atomic layer deposition process had the second highest 2Pr value as well as lower Dit values. Next, the thicknesses of Al2O3/Ge:HfO2 would be changed to 4/2 nm and 3/3 nm to investigate the ferroelectricity and leakage current. Although the 3-nm-thick Al2O3/3-nm-thick Ge:HfO2 shows a lower 2Pr value, the leakage current is much lower than 2-nm-thick Al2O3/2-nm-thick Ge:HfO2. The self-induced ferroelectric 3-nm-thick Ge:HfO2 thin film was then applied to fabricate Ge stacked nanowires gate-all-around field-effect transistor. The results show a steep subthreshold slope of 58 mV/dec for pFET and on-off current ratio > 105 and have high potential in low-power IC applications.

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Uniform 4-Stacked Ge_0.9Sn_0.1 Nanosheets Using Double Ge_0.95Sn_0.05 Caps by Highly Selective Isotropic Dry Etch

Cited by 16 publications

References 23 publications

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Self-Induced Ge-Doped HfO₂ Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O₃ Treatment with GeO₂ as Interfacial Layer

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Uniform 4-Stacked Ge0.9Sn0.1 Nanosheets Using Double Ge0.95Sn0.05 Caps by Highly Selective Isotropic Dry Etch

Cited by 16 publications

References 23 publications

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

Fabrication and performance of highly stacked GeSi nanowire field effect transistors

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Self-Induced Ge-Doped HfO2 Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O3 Treatment with GeO2 as Interfacial Layer

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Product

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About

Uniform 4-Stacked Ge_0.9Sn_0.1 Nanosheets Using Double Ge_0.95Sn_0.05 Caps by Highly Selective Isotropic Dry Etch

Self-Induced Ge-Doped HfO₂ Applied to Ge Stacked Nanowires Ferroelectric Gate-All-Around Field-Effect Transistor with Steep Subthreshold Slope Under O₃ Treatment with GeO₂ as Interfacial Layer