Unifying mesh- and tree-based programmable interconnect

Abstract

Abstract-We examine the traditional, symmetric, Manhattan mesh design for field-programmable gate-array (FPGA) routing along with tree-of-meshes (ToM) and mesh-of-trees (MoT) based designs. All three networks can provide general routing for limited bisection designs (Rent's Rule with 1) and allow locality exploitation. They differ in their detailed topology and use of hierarchy. We show that all three have the same asymptotic wiring requirements. We bound this tightly by providing constructive mappings between routes in one network and routes in another. For example, we show that a ( ) MoT design can be mapped to a (2 ) linear population ToM and introduce a corner turn scheme which will make it possible to perform the reverse mapping from any ( ) linear population ToM to a (2 ) MoT augmented with a particular set of corner turn switches. One consequence of this latter mapping is a multilayer layout strategy for -node, linear population ToM designs that requires only 2( ) two-dimensional area for any when given sufficient wiring layers. We further show upper and lower bounds for global mesh routes based on recursive bisection width and show these are within a constant factor of each other and within a constant factor of MoT and ToM layout area. In the process we identify the parameters and characteristics which make the networks different, making it clear there is a unified design continuum in which these networks are simply particular regions.Index Terms-Butterfly fat tree (BFT), fat pyramid, fat tree, field-programmable gate-array (FPGA), hierarchical, hierarchical synchronous reconfigurable array (HSRA), interconnect, Manhattan, mesh, mesh-of-trees (MoT), multilevel metallization, Rent's rule, tree-of-meshes (ToM).

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

“…Previous works [10][11][12], also confirms the multilevel BFT based 2D interconnect topology is able to reduce 59 % of the total number of switches and save 56 % of the total FPGA area compared to Mesh-based FPGA with identical logic density and array size [10]. Considering the challenges associated with 2D physical design of Tree-based FPGA [13,14], we proposed two different network partitioning methodology to design and implement high density 3D FPGAs based on Tree-based interconnect network. The main focus of this chapter is on the discussion of the complete set of tools and technologies needed to conduct 3D design feasibility study and interconnect network characterization methodologies to build high performance 3D re-configurable systems based on Tree-based interconnect and a comparison procedure has been put in place and the end to validate the advantages of 3D Tree-based FPGA over 3D Mesh-based FPGA architectures.…”

Field-Programmable Wiring Systems

“…10. A variety of heuristic strategies have been applied to counter the quadratic growth, such as fat tree, mesh of trees (MoT), and tree of meshes (ToM) implementations [33]. Most of the approaches replace a bruteforce crosspoint [ Fig.…”

“…Techniques from survivable network design can provide a framework that supports recovery from connection failures [8], [67]. Effective digital signal topologies such as the methods described by DeHon [33] will need to be extended to support multidomain fabrics.…”

Design of FPGA interconnect for multilevel metallization

“…4). The number of tree levels is (21) where is the length of each row or column. The number of channels, , composing the root level, , of each tree will thus be (22) The total bisection width at this level is the aggregate channel capacity across all channels across the chip…”

“…For the MoT, the level is defined by the size of the device (21). The total number of wires in a channel is then (27) Equation (22) told us how to calculate for the case.…”