Universal description of hot-carrier-induced interface states in NMOSFETs

Woltjer,; Paulzen,

doi:10.1109/iedm.1992.307418

Cited by 19 publications

(12 citation statements)

References 7 publications

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“…In some cases, channel hot electron injection (programming condition), and band-to-band tunneling induced hot hole injection (erasing condition) are used [22][23][24]. Trapping of charge via HCI could decrease the general reliability of a Metal-Oxide-Semiconductor Field-Effect Transistor MOSFET device [25][26][27] and likewise, the reliability of a FET-based memory device after overstressing the charge trapping layer with this mechanism. In this work, we are able to inject electronic charge to the np-HfO 2 trapping layer after applying a small gate electric field only (without using any HCI mechanism) so that a memory device with enhanced reliability is expected.…”

Section: Resultsmentioning

confidence: 99%

HfO2 nanoparticles embedded within a SOG-based oxide matrix as charge trapping layer for SOHOS-type memory applications

Molina

Ortega

Calleja

et al. 2012

Journal of Non-Crystalline Solids

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Section: Resultsmentioning

confidence: 99%

HfO2 nanoparticles embedded within a SOG-based oxide matrix as charge trapping layer for SOHOS-type memory applications

Molina

Ortega

Calleja

et al. 2012

Journal of Non-Crystalline Solids

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“…Our database includes a range of channel lengths, as well as a large number of stress conditions, varying in both V GS and V DS . Whereas the best measure of ISG from I-V characteristics would seem to be ∆(1/g mlin,max ) [4], [20], the parameter ∆(1/I ON ) (where I ON = I D @ V GS = V DS = technology power-supply voltage V TECH ) proved to be much more robust over the entire range of stress conditions and channel lengths in the database. However, this damage metric displayed additional channel-length (L) and threshold-voltage (V T ) dependences.…”

Section: Methodsmentioning

confidence: 96%

The energy-driven paradigm of NMOSFET hot-carrier effects

Rauch

Rosa

2005

IEEE Trans. Device Mater. Relib.

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As negative-MOSFET (NMOSFET) size and voltage are scaled down, the electron-energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high-field region. A new paradigm, or underlying concept, of NMOSFET hot-carrier behavior is proposed here, in which the fundamental "driving force" is available energy, rather than peak lateral electric field, as it is in the lucky electron model (LEM). The new prediction of the energy-driven paradigm is that the bias dependence of the impact-ionization (II) rate and hot-carrier lifetime is, to the first order, given by the energy dependences of the II scattering rate S II (E) and an effective interface state generation (ISG) cross section S IT (E), whereas, under the LEM, these bias dependences are determined by the number of electrons with energy above the II and ISG "threshold energies." This approach allows an experimental determination of S IT .

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“…It is assumed that the existing oxide electric field dependent -model [32] is suitable for expressing the CHE lifetime, because the physical basis of the model is the hot electron injection alone, and because the model can express the repulsive field dependence of the hot electron injection at the drain edge. The -dependent -model formula is expressed as…”

Section: A Modeling Of Channel Hot Electron Lifetimementioning

confidence: 99%

A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

Koike

Tatsuuma

2004

IEEE Trans. Device Mater. Relib.

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A simple and physical drain avalanche hot carrier lifetime model has been proposed. The model is based on a mechanism of interface trap generation caused by recombination of hot electrons and hot holes. The lifetime is modeled as. The formula is different from the conventional -sub model in that the exponent of is 2, which results from the assumed mechanism of the two-carrier recombination. It is shown that the mechanism gives a physical basis of the empirical -sub model for NMOSFETs. The proposed model has been validated experimentally both for NMOSFETs and for PMOSFETs. Model parameters extracted from experimental data show that carrier critical energies for creating damage are lower than the interface potential barriers. It is supposed that oxide band edge tailing enables low-energy carriers to create the damage. The channel hot electron condition becomes the worst case in short channel NMOSFETs, because gate voltage dependence of the maximum channel electric field decreases.

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Universal description of hot-carrier-induced interface states in NMOSFETs

Cited by 19 publications

References 7 publications

HfO2 nanoparticles embedded within a SOG-based oxide matrix as charge trapping layer for SOHOS-type memory applications

HfO2 nanoparticles embedded within a SOG-based oxide matrix as charge trapping layer for SOHOS-type memory applications

The energy-driven paradigm of NMOSFET hot-carrier effects

A Drain Avalanche Hot Carrier Lifetime Model for n- and p-Channel MOSFETs

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