Unrolling Ternary Neural Networks

Abstract

The computational complexity of neural networks for large scale or real-time applications necessitates hardware acceleration. Most approaches assume that the network architecture and parameters are unknown at design time, permitting usage in a large number of applications. This paper demonstrates, for the case where the neural network architecture and ternary weight values are known a priori, that extremely high throughput implementations of neural network inference can be made by customising the datapath and routing to remove unnecessary computations and data movement. This approach is ideally suited to FPGA implementations as a specialized implementation of a trained network improves efficiency while still retaining generality with the reconfigurability of an FPGA. A VGG style network with ternary weights and fixed point activations is implemented for the CIFAR10 dataset on Amazon's AWS F1 instance. This paper demonstrates how to remove 90% of the operations in convolutional layers by exploiting sparsity and compile-time optimizations. The implementation in hardware achieves 90.9 ± 0.1% accuracy and 122 k frames per second, with a latency of only 29 µs, which is the fastest CNN inference implementation reported so far on an FPGA.

AVNC: Attention-Based VGG-Style Network for COVID-19 Diagnosis by CBAM

“…After investigating through the recent VGG networks, we propose a similar VGG-style base network (VSBN) model for our task. Note that VGG-style are popularly used in many recent networks, such as References [19,20]. 2a), After the 1 st convolution block (CB), which consists of two repetitions of 2 convolutional layers with 64 kernels with sizes of 3 × 3, abbreviate as 2x(64 3x3), and one max pooling layers, the output is 112 × 112 × 64 (See S2 in Figure 2a).…”

LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors

“…This work splits the whole GNN into several sub-layers and adopts a layer-wise hardware architecture [12,2,13,16] to map all the sub-layers on-chip which is flexible and able to take full advantage of the customizability of FPGAs. In addition, we perform the calculation for different sublayers on their own units using dedicated optimization to achieve low latency and high design throughput.…”

“…This work proposes a custom Low Latency (LL)-GNN hardware architecture based on a layer-wise tailor-made pipeline to accelerate the GNNs for particle detectors, using the GNN-based JEDI-net algorithm as an end-to-end application. The layer-wise architecture has been used to speedup CNNs [12,13,14,15,16] and RNNs [17], but few studies focus on accelerating GNNs. First, we propose custom strength reduction for matrix operations based on the character of interaction-network based GNNs with a fully connected graph as an input, which avoids the expensive matrix multiplications of the adjacency matrix with the input feature matrix.…”

Ternary Hashing

“…However, these methods only quantize network weights into three values and network outputs are still kept as real-valued variables. Recent studies on hardware implementation of ternary neural network [1,24,20] also shown that it is possible to have an efficient and fast ternary-based computation on Field-Programmable Gate Array (FPGA) [3].…”