UPPAAL in Practice: Quantitative Verification of a RapidIO Network

Abstract

Abstract. Packet switched networks are widely used for interconnecting distributed computing platforms. RapidIO (Rapid Input/Output) is an industry standard for packet switched networks to interconnect multiple processor boards. Key performance metrics for these platforms include average-case and worst-case packet transfer latencies. We focus on verifying such quantitative properties for a RapidIO based multiprocessor platform that executes a motion control application. A performance model is available in the Parallel Object-Oriented Specification Language (POOSL) that allows for simulation based estimation results. It is however required to determine the exact worst-case latency as the application is time-critical. A model checking approach has been proposed in our previous work which transforms the POOSL model into an UPPAAL model. However, such an approach only works for a fairly small system. We extend the transformation approach with various heuristics to reduce the underlying state space, thereby providing an effective approximation approach that scales to industrial problems of a reasonable complexity.

Discretization of Continuous Dynamical Systems Using UPPAAL

“…A simple pragmatic way of doing this is by turning the calculated delay times T i into intervals of possible delay times [T L i , T U i ] (where L stands for Lower and U stands for Upper). One might interpret such an interval as a uniform distribution of delay times (this approach was used for performance analysis in [39]). In the ANIMO tool in Section 6 such intervals are created by asking the user to specify an uncertainty percentage, say 10%, and then defining T L = 0.9•T and T U = 1.1 • T .…”

The Event-B Modelling with Operators-based Refinement of NoC-based Wireless Sensors Networks

“…The Ant Colony Optimization, with the ability to search for paths, the NoC algorithms were called REAS (routing based on EAS [33]) and RACS (routing based on ACS 40) are tested and verified using simulations [35] ,with the ant algorithms , nodes are being able to find routes with latency less than that obtained with XY and OE algorithms, but simulations still take significant time to implement applications mapped on the network, showing its use in examples closer to real world NoCs. Besides those works, UML(Unified Modeling Language) and especially MARTE( Modeling and Analysis of Real-Time Embedded systems ) is used to analyse the three-axis classification scheme that used to classify a reconfigurable approach by the community [28,29,36]for the reconfiguration (exo-reconfigurable or endo-reconfigurable, dynamic or static, full or partial). Final mention of the formal verification for the algorithm of recovering in the networks by proposing new rules using formal methods such as using Switches algebra [37].…”

Timing analysis of First-Come First-Served scheduled interval-timed Directed Acyclic Graphs

“…Initially, task t 1 is the only enabled task, at [0, 0]. Completion of t 1 at [1, 1] enables t 2 , t 3 and t 4 , which then complete at [3,6], [4,7] and [4,10] respectively. Now, tasks t 5 , t 6 and t 7 are enabled at [3,6], [5,7] and [4,10].…”