URECA: Unified register file for CGRAs

Dave, Shail; Balasubramanian, M.; Shrivastava, Aviral

doi:10.23919/date.2018.8342172

Cited by 7 publications

(3 citation statements)

References 15 publications

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“…This paper focuses on methods to solve the mapping problem, which combines two NP-complete problems: scheduling and binding. This raises CGRA compilation as a unique scientifique problem and main challenge, because mapping might fail [23]- [25], which is of course unconceivable from the user point of view. To this end, for instance, HiMap [26] is an iterative algorithm that terminates when a valid mapping is found.…”

Section: Problem Formulationmentioning

confidence: 99%

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Twenty Years of Automated Methods for Mapping Applications on CGRA

Martin

2022

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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Coarse-GrainedReconfigurable Architectures (CGRAs) emerged about 30 years ago. The very first CGRAs were programmed manually. Fortunately, some compilation approaches appeared rapidly to automate the mapping process. Numerous surveys on these architectures exist. Other surveys also gather the tools and methods, but none of them focuses on the mapping process only. This paper focuses solely on automated methods and techniques for mapping applications on CGRA and covers the last two decades of research. This paper aims at providing the terminology, the problem formulation, and a classification of existing methods. The paper ends with research challenges and trends for the future.

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Section: Problem Formulationmentioning

confidence: 99%

“…The internal memory resources of the CGRA should also be used efficiently. Register allocation is presented in [29], [46], for a rotating register file [29], or for a unified register file [25].…”

Section: Data Mappingmentioning

confidence: 99%

Twenty Years of Automated Methods for Mapping Applications on CGRA

Martin

2022

2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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“…Such an approach is beneficial to accelerating non-vectorizable loops through instruction-level parallelism. However, these mapping techniques were primarily evaluated for kernels with relatively small computational or memory requirements and on considerably smaller PE arrays [33,35,36]. In contrast, high-performance demanding kernels of gemm, convolutions, logistic regressions, etc.…”

Section: Related Workmentioning

confidence: 99%

dMazeRunner

Dave

Kim

Avancha

et al. 2019

ACM Trans. Embed. Comput. Syst.

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Dataflow accelerators feature simplicity, programmability, and energy-efficiency and are visualized as a promising architecture for accelerating perfectly nested loops that dominate several important applications, including image and media processing and deep learning. Although numerous accelerator designs are being proposed, how to discover the most efficient way to execute the perfectly nested loop of an application onto computational and memory resources of a given dataflow accelerator ( execution method ) remains an essential and yet unsolved challenge. In this paper, we propose dMazeRunner -- to efficiently and accurately explore the vast space of the different ways to spatiotemporally execute a perfectly nested loop on dataflow accelerators (execution methods). The novelty of dMazeRunner framework is in: i) a holistic representation of the loop nests, that can succinctly capture the various execution methods, ii) accurate energy and performance models that explicitly capture the computation and communication patterns, data movement, and data buffering of the different execution methods, and iii) drastic pruning of the vast search space by discarding invalid solutions and the solutions that lead to the same cost. Our experiments on various convolution layers (perfectly nested loops) of popular deep learning applications demonstrate that the solutions discovered by dMazeRunner are on average 9.16× better in Energy-Delay-Product (EDP) and 5.83× better in execution time, as compared to prior approaches. With additional pruning heuristics, dMazeRunner reduces the search time from days to seconds with a mere 2.56% increase in EDP, as compared to the optimal solution.

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