Use of charge sharing to reduce energy consumption in wide fan-in gates

Khellah, Muhammad; Elmasry, M.I.

doi:10.1109/iscas.1998.706788

Cited by 23 publications

(8 citation statements)

References 4 publications

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“…Low Swing Scheme One method of reducing the ML power consumption, and potentially increasing its speed, is to reduce the ML voltage swing [4], [5]. In the case of a miss, the match line discharges through the CAM cell(s) to ground, whereas in the case of match, the match line remains at the precharge level.…”

Section: Match Line Sensing Schemementioning

confidence: 99%

Performance Comparison of Positive Feedback Match-Line (ML) Sensing Schemes for Low Power TCAM

Rahaman¹,

Islam²

2016

International Journal of Innovative Research in Electrical, Ele

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This paper presents a comparative performance analysis among different positive feedback based match line (ML) sensing scheme such as Mismatch dependent, Active feedback and Resistive feedback scheme. The comparison has been done based on parameters like search time, voltage margin, peak dynamic power and worst case energy consumption. Although most popular ML sensing scheme Current Race (CR) consumes more power than positive feedback based ML sensing scheme but performance comparison has also been shown between CR with each of three positive feedback based match line (ML) sensing scheme for equal search time. Finally, for search time Resistive feedback, for voltage margin and peak dynamic power consumption Mismatch dependent and for worse case energy consumption Active feedback scheme were found to be showing the best performance. For performance comparison the all the circuits is simulated using 130nm 1.2V CMOS logic.

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Section: Match Line Sensing Schemementioning

confidence: 99%

Performance Comparison of Positive Feedback Match-Line (ML) Sensing Schemes for Low Power TCAM

Rahaman¹,

Islam²

2016

International Journal of Innovative Research in Electrical, Ele

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“…Energy reduction is achieved by reduction of TCAM array size. Charge sharing techniques use either a separate capacitor [9], [10] or segment(s) of the ML [11], [12] to store charge in the precharge or partial comparison phase, respectively. This charge is shared with the ML or remaining ML segment(s) in the next phase.…”

Section: Previous Workmentioning

confidence: 99%

“…This charge is shared with the ML or remaining ML segment(s) in the next phase. Techniques in [9], [10] are often referred to as low swing schemes as they reduce the ML power by reducing the ML swing voltage. But they suffer from the problem of low noise margin and area penalty arising from the extra capacitor.…”

Section: Previous Workmentioning

confidence: 99%

An Energy Efficient Design of High-Speed Ternary CAM Using Match-Line Segmentation and Resistive Feedback in Sense Amplifier

Ali

Islam²

2012

JCP

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Abstract-This paper presents a high-speed and low-energy match line (ML) sensing scheme for ternary content addressable memory (TCAM). The proposed sensing scheme employs selective precharge which performs partial comparison on the TCAM words to eliminate most of the mismatched words from further comparison. Use of positive feedback in the sense amplifiers engaged in this phase speeds up search operation and reduces energy consumption. In the next phase, remaining portions of those words which were matched in the first phase are scanned to find the fully matched words. Lower resistance in the charging path of the sense amplifier in the second phase causes fast match detection. The proposed technique is simulated using 130nm 1.2V CMOS logic. Compared to conventional current-race (CR) sensing scheme the proposed scheme shows 26.5% speed enhancement and at least 31% energy reduction at the cost of insignificant area overhead and small voltage margin degradation. Unlike many CR type schemes, no analog control voltage has been used in the proposed scheme.

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“…The reduction of power consumption is linearly proportional to the reduction of voltage swing. Such technique has been applied in [12,13] where the ML swing is reduced from the full supply swing to 300mV. The challenge with such method, that it may require another voltage supply to generate the low-swing voltage.…”

Section: Low-swing Schemementioning

confidence: 99%

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

Deptuch¹,

Hoff²,

Kwan³

et al. 2010

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Executive SummaryFuture particle physics experiments looking for rare processes will have no choice but to address the demanding challenges of fast pattern recognition in triggering as detector hit density becomes significantly higher due to the high luminosity required to produce the rare process. We propose to develop a 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) chip for HEP applications, to advance the state-of-the-art for pattern recognition and track reconstruction for fast triggering.3D technology is the integration of thinned and bonded silicon integrated circuits with vertical interconnects between IC layers using through silicon vias (TSVs). The technology has wide applications in industry, ranging from memories to pixel arrays to microprocessors and FPGAs. Performance can be improved significantly by reducing interconnect R/L/C for higher speed and density. In addition, it provides the freedom to divide functionality among tiers to create new designs that are simply not possible in 2D. As Moore's law is approaching severe limitations, it is expected that 3D technology will be the next scaling engine. Generally speaking, 3D technology becomes useful when a task can be partitioned into multiple sections that are physically and logically separable, and the interconnections among them are straightforward. Moreover, the use of 3D technology can have varied goals. For example, it can be used to increase transistor density -i.e. to increase the number of transistors per square micron. Such is a major goal of 3D DRAM design. Here, the DRAM task is first logically divided into a control/interface section and memory core. The control/interface section is physically separated onto its own tier, and the memory core is further divided into memory banks which are each vertically integrated onto their own tiers. A second, different example is the 3D integration of microprocessor systems. Here, different functions that have been traditionally separated can be brought together in a single monolithic structure and technological limitations can be eliminated. CPU and memory can be placed on separate tiers and the interconnect between them -i.e. the memory bus -can be reduced from on the order of tens of millimeters (a bus on a PC board) to a few tens of microns (the length of a through silicon via). Also, the memory bus itself can be expanded from a few bits to hundreds of bits wide, dramatically improving the memory access bandwidth.With Pattern Recognition Associative Memory for HEP tracking trigger applications, the task is indeed logically and physically dividable and the interconnections among them are straightforward, making it a good candidate for 3D integration. Associative Memories, in HEP, are based on the concept of a Content Addressable Memory (CAM) -memory that is not accessed by providing the memory cell with an appropriate address, but rather a memory that is accessed by providing the memory cell with some related content. In the case of tracking triggers in HEP, that content ...

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Use of charge sharing to reduce energy consumption in wide fan-in gates

Cited by 23 publications

References 4 publications

Performance Comparison of Positive Feedback Match-Line (ML) Sensing Schemes for Low Power TCAM

Performance Comparison of Positive Feedback Match-Line (ML) Sensing Schemes for Low Power TCAM

An Energy Efficient Design of High-Speed Ternary CAM Using Match-Line Segmentation and Resistive Feedback in Sense Amplifier

Proposal for the development of 3D Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

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