Use of minimum-adder multiplier blocks in FIR digital filters

Dempster, Andrew G.; Macleod, M.D.

doi:10.1109/82.466647

Cited by 509 publications

(434 citation statements)

References 20 publications

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“…As the coefficients of the subfilters are fixed, they can be realized using sum-of-power-of-two (SOPOT) coefficients or canonical signed digit in stead of expensive general-purpose multipliers [17,19]. In addition, if the subfilters are implemented as their transposed form, the redundancy in realizing the multiplications of these SOPOT coefficients can be significantly reduced by means of a multiplier-block technique [25], which gives rise to minimum adder realization. In this paper, we shall mainly focus on the approximation of fractional delay operation using VFDDFs, because of their numerous advantages mentioned above.…”

Section: Fractional Delay Digital Filtersmentioning

confidence: 99%

A Versatile Iterative Framework for the Reconstruction of Bandlimited Signals from Their Nonuniform Samples

Tsui

Chan

2010

J Sign Process Syst

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In this paper, we study a versatile iterative framework for the reconstruction of uniform samples from nonuniform samples of bandlimited signals. Assuming the input signal is slightly oversampled, we first show that its uniform and nonuniform samples in the frequency band of interest can be expressed as a system of linear equations using fractional delay digital filters. Then we develop an iterative framework, which enables the development and convergence analysis of efficient iterative reconstruction algorithms. In particular, we study the Richardson iteration in detail to illustrate how the reconstruction problem can be solved iteratively, and show that the iterative method can be efficiently implemented using Farrow-based variable digital filters with few general-purpose multipliers. Under the proposed framework, we also present a completed and systematic convergence analysis to determine the convergence conditions. Simulation results show that the iterative method converges more rapidly and closer to the true solution (i.e. the uniform samples) than conventional iterative methods using truncation of sinc series.

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Section: Fractional Delay Digital Filtersmentioning

confidence: 99%

A Versatile Iterative Framework for the Reconstruction of Bandlimited Signals from Their Nonuniform Samples

Tsui

Chan

2010

J Sign Process Syst

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“…6, together with the realization in Fig. 9 a total of 33 adders are required for the multiplier block using the RAG-n algorithm in [45]. This is an optimal result since there are 33 different (odd) coefficients as discussed in [58], and, hence, there is no need to apply the slightly more efficient algorithms in [47][48][49].…”

Section: Example and Comparisonsmentioning

confidence: 90%

“…Efficient realization of constant multiplications is an active research area and much effort has been focused on the case where one input data is multiplied by several constant coefficients. This problem has mainly been motivated by single-rate FIR filters, where for a transposed direct form FIR filter the input is multiplied by several coefficients, see [45][46][47][48][49]. The resulting implementation of several multiplications is denoted multiplier block, as in [45].…”

Section: Multiple-constant Multiplication Techniques For the Subfiltementioning

confidence: 99%

Two-Rate Based Structures for Computationally Efficient Wide- Band FIR Systems

Johansson¹,

Gustafsson²

2013

Digital Filters and Signal Processing

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“…Ref. [4] nominates RAG (reduced adder graph) algorithm, using the look-up table in [3] to minimize the adder cost of a multiplier block. This algorithm consists of two parts, optimum search and heuristic result completion.…”

Section: Introductionmentioning

confidence: 99%

Minimizing the adder cost in multiple constant multipliers

Omam

Fakhraie

Shoaei

2006

IEICE Electron. Express

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Abstract:The hardware complexity of digital filters is mainly dominated by the coefficient multipliers. Implementing fixed-point coefficient multiplication as a network of adders, subtractors, and shifters, yields lower power consumption. In such filters the number of adders (and subtractors) determines the implementation cost. The reason is that shifts are implemented as hard-wired inter-block connections and are considered "free". In transposed implementation of an FIR filter, each input is multiplied by several coefficients. Considering all the coefficients as a multiplier block and omitting the redundancies by sharing the common fundamentals among different coefficients, yields great reduction in the number of arithmetic operations. This paper presents a graph based algorithm to reduce the computational complexity of multiple constant multiplications. Simulation results show that using the proposed method results good improvement in adder cost of multiplier blocks. Keywords: digital filter, adder cost, graph representation Classification: Integrated circuits References[1] A. G. Dempster and M. D. Macleod, "Using all signed-digit representations to design single integer multipliers using subexpression elimination,"

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Use of minimum-adder multiplier blocks in FIR digital filters

Cited by 509 publications

References 20 publications

A Versatile Iterative Framework for the Reconstruction of Bandlimited Signals from Their Nonuniform Samples

A Versatile Iterative Framework for the Reconstruction of Bandlimited Signals from Their Nonuniform Samples

Two-Rate Based Structures for Computationally Efficient Wide- Band FIR Systems

Minimizing the adder cost in multiple constant multipliers

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