Use of Multicore Processors in Avionics and its Potential Impact on Implementation and Certification

Kinnan, L.

doi:10.4271/2009-01-3261

Cited by 7 publications

(5 citation statements)

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“…However, the multi-core integration (multi-IMA) of legacy single-core IMA systems is a certification challenge, because legacy partitions temporal and spatial isolation must be guaranteed without incurring in huge re-certification costs [165,166,167,24,168,169,170,171]. The updated ARINC 653 supports the usage of multi-core devices but restricting the execution of safety partitions to a single core at a time with the remaining cores disabled, which is against SWaP reduction.…”

Section: Avionics Domainmentioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Section: Avionics Domainmentioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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“…All this concerns result in the fact that the development of mixed-criticality systems based on multicore architectures and virtualization technology is not a trivial task [28], [29], [30], [31], because it implies providing sufficient evidences of isolation, separation and independence, which in turn must be provided to a certification body for guaranteeing that the system is safe enough for its purpose.…”

Section: Related Workmentioning

confidence: 99%

Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning

Larrucea

Agirre

Nicolás

et al. 2015

2015 Forum on Specification and Design Languages (FDL)

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The transition from conventional federated embedded system architectures to mixed-criticality integrated multicore architectures provides benefits in terms of cost, size, weight, scalability and reliability. As a consequence, integrated mixedcriticality solutions are an objective for many embedded systems developers, although the challenges related with the safety certification of multicore approaches may hinder their adoption.Among many other stringent requirements, the safety standards demand to prove that the mixed-criticality systems are free of interferences, thus ensuring the spatial and temporal interdependence among applications. This paper contributes with a measured based temporal independence validation of a partitioned multicore mixed-criticality system.

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“…Literature on multicore certification is mainly concerned with ensuring timing guarantees without incurring undue resource over provisioning [3], [14], [23], [24]. The design of time deterministic processors and hardware-based separation is considered in [6], as a means to simplify the collection of evidence required for a certification process by providing predictable timing guarantees by design.…”

Section: Related Workmentioning

confidence: 99%

On the tailoring of CAST-32A certification guidance to real COTS multicore architectures

Agirre

Abella

Azkarate-Askasua

et al. 2017

2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)

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The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction. Yet, the unpredictable impact on timing of contention in shared hardware resources challenges certification. Furthermore, most safety certification standards target single-core architectures and do not provide explicit guidance for multicore processors. Recently, however, CAST-32A has been presented providing guidance for software planning, development and verification in multicores. In this paper, from a theoretical level, we provide a detailed review of CAST-32A objectives and the difficulty of reaching them under current COTS multicore design trends; at experimental level, we assess the difficulties of the application of CAST-32A to a real multicore processor, the NXP P4080.

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Use of Multicore Processors in Avionics and its Potential Impact on Implementation and Certification

Cited by 7 publications

References 0 publications

Multi-core Devices for Safety-critical Systems

Multi-core Devices for Safety-critical Systems

Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning

On the tailoring of CAST-32A certification guidance to real COTS multicore architectures

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