2003
DOI: 10.1117/12.485001
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Use of silicon-versus-layout verification (SiVL) in process control of wafer lithography and mask-making metrology

Abstract: The latest generations of CMOS are increasingly being patterned closer to the resolution limits of optical lithography, which is one of the reasons that their process windows are decreasing. Hence, control of the process gets more and more important and in-die critical-dimension (CD) measurements are gradually being introduced for the monitoring of the in-line lithographic process performance. Because an increasingly large portion of the CD-error-budget is already being consumed by the mask-making, there is al… Show more

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