Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Rogers, Brian; Chhabra, Siddhartha; Prvulovic, Milos; Yan, Shuicheng

doi:10.1109/micro.2007.4408255

Cited by 40 publications

(82 citation statements)

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“…Secure processor has been extensively studied during the last decade [18], [19], [20], [41], [42], [43], [44], [45], [46], [47], [22], [21]. For example, Bastion [22] and SecureME [21] also leverage secure processor to protect against hardware attacks.…”

Section: Secure Processormentioning

confidence: 99%

“…In contrast, Kite retains OS and application transparency by leveraging the VM-Shim mechanism. For secure processor designs, we adapt two major techniques: AISE (Address Independent Seed Encryption) based data encryption and Bonsai Merkle Tree (BMT) [45] to secure off-chip data. Briefly, AISE and BMT are used to ensure privacy and integrity accordingly.…”

Section: Secure Processormentioning

confidence: 99%

“…Briefly, AISE and BMT are used to ensure privacy and integrity accordingly. More details could be found in [45].…”

Section: Secure Processormentioning

confidence: 99%

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Secure Outsourcing of Virtual Appliance

Xia

Liu

Guan

et al. 2017

IEEE Trans. Cloud Comput.

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Computation outsourcing using virtual appliance is getting prevalent in cloud computing. However, with both hardware and software being controlled by potentially curious or even malicious cloud operators, it is no surprise to see frequent reports of security accidents, like data leakages or abuses. This paper proposes Kite, a hardware-software framework that guards the security of tenant's virtual machine (VM), in which the outsourced computation is encapsulated. Kite only trusts the processor and makes no security assumption on external memory, devices, or hypervisor. Unlike prior hardware-based approaches, Kite retains transparency with existing VM and requires few changes to the (untrusted) hypervisor by introducing VM-Shim mechanism. Each VM-Shim instance runs in between its VM and the hypervisor, which only transfers necessary information designated by the VM to the hypervisor and external environments. Kite also considers the high-level semantic of interaction between VM and hypervisor to defend against attacks through legitimate operations or interfaces. We have implemented a prototype of Kite's secure processor in a QEMU-based full-system emulator and its software components on real machine. Evaluation shows that the performance overhead of Kite ranges from 0.5%-14.0% on simulated platform and 0.4%-7.3% on real hardware.

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Section: Secure Processormentioning

confidence: 99%

Section: Secure Processormentioning

confidence: 99%

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Secure Outsourcing of Virtual Appliance

Xia

Liu

Guan

et al. 2017

IEEE Trans. Cloud Comput.

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“…If an attacker has physical access to hardware (e.g., a malicious cloud operator), we have already seen that data encryption is an important first step. Even with data encryption, the attacker can still engage in replay attacks [29] (returning the old encrypted value of data to disrupt the application) or gather sensitive information [13], [17] by snooping on the address trace (note that addresses are still sent out in plain text). To address these vulnerabilities, researchers have constructed solutions, Merkle trees [12] and oblivious RAM [40], respectively, that organize memory blocks into a logical tree structure and require fetching all the blocks in a given subtree.…”

Section: Securitymentioning

confidence: 99%

Making the Case for Feature-Rich Memory Systems: The March Toward Specialized Systems

Balasubramonian

2016

IEEE Solid-State Circuits Mag.

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“…Additional optimizations have been proposed to further reduce the overheads. Using GMAC in place of a hash function lowers the overheads to around 5% even with encryption [33] and Bonsai Merkle Trees report the overhead of 2% using small trees [27].…”

Section: Cached Hash Treesmentioning

confidence: 99%

Ivec

Huang

Suh

2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

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This paper proposes a unified off-chip memory integrity protection scheme, named IVEC. Today, a system needs two independent mechanisms in order to protect the memory integrity from both physical attacks and random errors. Integrity verification schemes detect malicious tampering of memory while error correcting codes (ECC) detect and correct random errors. IVEC enables both detection of malicious attacks for security and correction of random errors for reliability at the same time by extending the integrity verification techniques. Analytical and experimental studies show that IVEC can correct single-bit errors and even multibit errors from one DRAM chip within a cache block read without any additional ECC bits, when the integrity verification is also required for security, effectively removing the memory and bandwidth overheads (12.5%) of typical ECC schemes. Alternatively, with parity bits, IVEC can provide even stronger error correction capabilities comparable to the traditional chip-kill correct, still with less overheads. For both cases, IVEC can use standard non-ECC DIMMs.

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Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly

Cited by 40 publications

References 0 publications

Secure Outsourcing of Virtual Appliance

Secure Outsourcing of Virtual Appliance

Making the Case for Feature-Rich Memory Systems: The March Toward Specialized Systems

Ivec

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