Using advanced compiler technology to exploit the performance of the Cell Broadband Engine™ architecture

Abstract

The continuing importance of game applications and other numerically intensive workloads has generated an upsurge in novel computer architectures tailored for such functionality. Game applications feature highly parallel code for functions such as game physics, which have high computation and memory requirements, and scalar code for functions such as game artificial intelligence, for which fast response times and a full-featured programming environment are critical. The Cell Broadband Enginee architecture targets such applications, providing both flexibility and high performance by utilizing a 64-bit multithreaded PowerPCt processor element (PPE) with two levels of globally coherent cache and eight synergistic processor elements (SPEs), each consisting of a processor designed for streaming workloads, a local memory, and a globally coherent DMA (direct memory access) engine. Growth in processor complexity is driving a parallel need for sophisticated compiler technology. In this paper, we present a variety of compiler techniques designed to exploit the performance potential of the SPEs and to enable the multilevel heterogeneous parallelism found in the Cell Broadband Engine architecture. Our goal in developing this compiler has been to enhance programmability while continuing to provide high performance. We review the Cell Broadband Engine architecture and present the results of our compiler techniques, including SPE optimization, automatic code generation, single source parallelization, and partitioning.

Adaptive Line Size Cache for Irregular References on Cell Multicore Processor

“…Figure 6 shows set masks of the long line address and short line address. Both the numbers of set in Tag Entry Array 1 and Tag Entry Array 2 are powers of 2, so a bit-wise AND operation instead of the hash function is used to improve performance, as shown in (1).…”

“…There has been substantial research [1][2][3][4][5][6] on software cache specifically for Cell processor. Eichenberger et al [1] propose a compiler-controlled software cache.…”

“…Eichenberger et al [1] propose a compiler-controlled software cache. It's a traditional 4-way set-associative cache implemented in software.…”

Importance of explicit vectorization for CPU and GPU software performance

“…Due to several well-documented GPU performance factors [5], it is common for GPU developers to become involved in many aspects of coding that can positively affect performance. CPU optimization, however, is usually left to the compiler, and it has been argued that compilers achieve high utilization of the CPU's computing power [6] [7].…”

Streaming Applications

“…These include the MultiCore Framework [23], Cell SuperScalar [21], and the Octopiler compiler [50]. The MultiCore Framework handles multidimensional data at the coprocessors.…”