Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Quinn, Heather; Robinson, William H.; Rech, Paolo; Aguirre, M.A.; Barnard, Arno; Desogus, Marco; Entrena, Luis; García-Valderas, M.; Guertin, S. M.; Kaeli, David; Kastensmidt, Fernanda Lima; Kiddie, Bradley T.; Sanchez-Clemente, Antonio; Reorda, M. Sonza; Sterpone, Luca; Wirthlin, Michael

doi:10.1109/tns.2015.2498313

Cited by 87 publications

(18 citation statements)

References 28 publications

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“…This section presents an analysis of the implementation results and describes the results of timing and fault injection performance experiments performed on TCLS-based design, TCLS design. We selected benchmark applications performing matrix multiplications, which are widely used in real-life applications [18], to evaluate the timing and fault-injection performance of the proposed TCLS approach. Within each benchmark application, several matrix multiplication operations are performed, in a bare-metal environment, on different The Unhardened Design version will run its applications on CPU0 only.…”

Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Kasap

Wächter

Zhai

et al. 2020

2020 IEEE Nordic Circuits and Systems Conference (NorCAS)

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An attractive option for realizing applications in radiation environments is to employ All-Programmable Systemon-Chips (APSoCs) thanks to their high-performance computing and power efficiency merits. Despite APSoC's advantages, like any other electronic device, they are prone to radiation effects. Processors found in APSoCs must, therefore, be adequately hardened against ionizing-radiation to become a viable alternative for harsh environments. This paper proposes a novel triple-core lockstep (TCLS) approach to secure the Xilinx Zynq-7000 APSoC dual-core ARM Cortex-A9 processor against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in Zynq's programmable logic (PL) layer. The proposed strategy uses software-level checkpointing principles along with roll-back and roll-forward mechanisms (i.e. software redundancy), and hardware-level processor replication as well as checker circuits (i.e. hardware redundancy). Results of fault injection experiments show that the proposed solution achieved high soft error security by mitigating about 99% of bit-flips injected into both ARM cores' register data.

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Section: Implementation and Experimental Resultsmentioning

confidence: 99%

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Kasap

Wächter

Zhai

et al. 2020

2020 IEEE Nordic Circuits and Systems Conference (NorCAS)

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“…This benchmark was selected for compliance with current efforts towards a common set of benchmarks that can be used for comparison among different experiments [18]. It also includes a set of pre-generated input vectors that were designed by the ATPG community to fully cover the functionality of the circuit.…”

Section: Resultsmentioning

confidence: 99%

Partial TMR in FPGAs Using Approximate Logic Circuits

Sanchez-Clemente

Entrena

García-Valderas

2015

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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“…System and Micro-architecture Metrics We characterize the system and micro-architectural behaviors [40] of the data motifs, which are significant for design and optimization [36]. For system evaluation, we report the metrics of CPU utilization, I/O Wait, disk For micro-architectural evaluation, we use the Top-Down analysis method [44], which categorizes the pipeline slots into four categories, including retiring, bad speculation, frontend bound and backend bound.…”

Section: Experiments Methodologymentioning

confidence: 99%

Data motifs

Gao

Zhan

Wang

et al. 2018

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques

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The complexity and diversity of big data and AI workloads make understanding them difficult and challenging. This paper proposes a new approach to modelling and characterizing big data and AI workloads. We consider each big data and AI workload as a pipeline of one or more classes of units of computation performed on different initial or intermediate data inputs. Each class of unit of computation captures the common requirements while being reasonably divorced from individual implementations, and hence we call it a data motif. For the first time, among a wide variety of big data and AI workloads, we identify eight data motifs that take up most of the run time of those workloads, including Matrix, Sampling, Logic, Transform, Set, Graph, Sort and Statistic. We implement the eight data motifs on different software stacks as the micro benchmarks of an open-source big data and AI benchmark suite -BigDataBench 4.0 perspective of data sizes, types, sources, and patterns as a lens towards fully understanding big data and AI workloads. We believe the eight data motifs are promising abstractions and tools for not only big data and AI benchmarking, but also domain-specific hardware and software co-design.

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Using Benchmarks for Radiation Testing of Microprocessors and FPGAs

Cited by 87 publications

References 28 publications

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Partial TMR in FPGAs Using Approximate Logic Circuits

Data motifs

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