Using contrapositive law in an implication graph

Abstract

Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new "oring" node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used "anding" node. An n-input gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication graph associated with anding and oring nodes. For the ISCAS'85 benchmark circuit c1908, the new graph identifies 5 out of a total of 7 redundant faults. The best known previous implication graph procedure could only identify 2 redundant faults. We analyze the unidentified redundant faults and suggest a possible improvement.

Diagnostic and Detection Fault Collapsing for Multiple Output Circuits

“…We have used an ATPG to find redundancies. There are recent methods [13,17,24] of redundancy identification, not based on ATPG but using non-exhaustive search, that are less time consuming. Their use may provide trade off between the CPU time efficiency of the algorithms and the smallest possible collapsed set found.…”

“…The column Functional is diagnostic equivalence collapsing set size and is compared with structural equivalence collapsing set obtained from the flattened circuit. Our collapsing program uses the update for computing transitive closure as described by Dave et al [13]. The CPU times reported in both cases are those of the same program so that we can make a better comparison for the two collapsing methods.…”