Using Design Hierarchy to Improve Quality of Results in FPGAs

Kaviani, Alireza

doi:10.1007/3-540-46117-5_104

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2012

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“…FPGA floor-planning case-studies do exist [4] [5] and demonstrate that area constraints can aid in achieving timing closure but these success stories mostly suggest that floor-planning is beneficial and provide little direction in general. Rather than examine a single design with a few floor-plan modifications, this work takes a different tack and focuses on the submodules themselves and how area and timing constraints ultimately affect their performance.…”

Section: Introductionmentioning

confidence: 95%

Profiling FPGA floor-planning effects on timing closure

Lamprecht

Hutchings

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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The impact of shape, area allocation and timing constraints on partitions was determined by selecting a standard set of submodules and performing over 1,000,000 place/route experiments. Place/route experiments used different area and timing constraints and their resulting trace reports provided timing results. These results suggest that the best results are obtained when about 20% additional area (above synthesis estimates) is allocated for each submodule. The aspect ratio of submodules is largely a non-issue (there was one exception in the data). In some cases, carefully constraining area dramatically improves results.

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Section: Introductionmentioning

confidence: 95%