Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits

Fey, Dietmar; Reichenbach, Marc; Soll, Christopher; Biglari, Mehrdad; Röber, Jürgen; Weigel, Robert

doi:10.1145/2989081.2989124

Cited by 16 publications

(10 citation statements)

References 16 publications

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“…there exist adders, that show only two discrete steps but require a much more complex logic what is caused by the fact that these adders are using operands to a base r ≥ 2. Details concerning this computer arithmetic stuff can be found in [4], [2].…”

Section: Ternary Addersmentioning

confidence: 99%

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Fey

2017

Preprint

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This paper investigates the potentials of using a hybrid memristor CMOS technology, called MeMOS, for the realisation of ternary adders. Ternary adders exploit the qualitative advantage of multi-value storage capability of memristors compared to conventional CMOS flip-flops storing only binary values in one cell. Furthermore they carry out an addition in O(1) and are therefore considered. The MeMOS approach is compared to a CMOS solution for the ternary adders using multi value memristors as registers concerning the achievable latency and the energy consumption. It is shown that using the TEAM, VTEAM model and a model considering commercially available memristors from Known the approach of using CMOS ternary adders using memristors as multi-value register memory is to prefer. MeMOS circuits have advantages for a static operation mode, i.e. if they are operated after a reset.

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Section: Ternary Addersmentioning

confidence: 99%

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Fey

2017

Preprint

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“…Using memristive devices for ternary arithmetic was first investigated by Fey (2014). On the basis of the work of Fey et al (2016), the improvement in the energy-delay product and area for a ternary adder circuitry using multi-bit registers based on memristors compared to SRAM-based solutions was shown. The architecture can be further enhanced by using memristorbased pipeline registers that make it possible to use homogeneous pipelines for not only the addition operation but also the subtraction and multiplication operations instead of superscalar pipelines that use different pipeline paths for various operations (Fey, 2015).…”

Section: Introductionmentioning

confidence: 99%

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms

Hosseinzadeh

Biglari

Fey

2021

Front. Nanotechnol.

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Non-volatile memory (NVM) technologies offer a number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, and, of course, the non-volatility and especially the qualitative advantage of multi-bit capability. It is expected that memristors based on resistive random access memories (ReRAMs), phase-change memories, or spin-transfer torque random access memories will replace conventional memory technologies in certain areas or complement them in hybrid solutions. To support the design of systems that use NVMs, there is still research to be done on the modeling side of NVMs. In this paper, we focus on multi-bit ternary memories in particular. Ternary NVMs allow the implementation of extremely memory-efficient ternary weights in neural networks, which have sufficiently high accuracy in interference, or they are part of carry-free fast ternary adders. Furthermore, we lay a focus on the technology side of memristive ReRAMs. In this paper, a novel memory model in the circuit level is presented to support the design of systems that profit from ternary data representations. This model considers two read methods of ternary ReRAMs, namely, serial read and parallel read. They are extensively studied and compared in this work, as well as the write-verification method that is often used in NVMs to reduce the device stress and to increase the endurance. In addition, a comprehensive tool for the ternary model was developed, which is capable of performing energy, performance, and area estimation for a given setup. In this work, three case studies were conducted, namely, area cost per trit, excessive parameter selection for the write-verification method, and the assessment of pulse width variation and their energy latency trade-off for the write-verification method in ReRAM.

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“…Fortunately, research activities to address problem (1) have been done before. To overcome it, the authors of [14] propose to use novel emerging memories technologies such as ReRAM, which are able to store multiple states in one memory cell and therefore drastically improve the memory density.…”

Section: Introductionmentioning

confidence: 99%

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

et al. 2021

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Redundant number systems (RNS) are a well-known technique to speed up arithmetic circuits. However, in a complete CPU, arithmetic circuits using RNS were only included on subcircuit level e.g. inside the Arithmetic Logic Unit (ALU) for realization of the division. Still, extending this approach to create a CPU with a complete data path based on RNS can be beneficial for speeding up data processing, due to avoiding conversions in the ALU between RNS and binary number representations. Therefore, with this paper we present a new CPU architecture called RISC-V3 which is compatible to the RISC-V instruction set, but uses an RNS number representation internally to speed up instruction execution times and therefore increase the system performance. RISC-V is very suitable for RNS because it does not have a flags register which is expensive to calculate when using an RNS. To present reliable performance numbers, arithmetic circuits using RNS were realized in different semiconductor technologies. Moreover, an instruction set simulator was used to estimate system performance for a benchmark suite (Embench). Our results show, that we are up to 81% faster with the RISC-V3 architecture compared to a binary one, depending on the executed benchmark and CMOS technology.

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Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits

Cited by 16 publications

References 16 publications

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

Evaluating Ternary Adders using a hybrid Memristor / CMOS approach

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms

RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems

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