Using MIC to Accelerate a Typical Data-Intensive Application: The Breadth-first Search

Abstract

Data-intensive applications draw more and more attentions in the last few years. The breadth-first search (BFS), a typical data-intensive application, is so widely used that the Graph 500 benchmark uses it to rank supercomputers' performance. The Intel MIC (Many Integrated Core), which is designed for highly parallel computing, hasn't been fully evaluated for data-intensive applications. In this paper, we discuss how to use MIC to accelerate the BFS. Optimizations both for native mode and for offload mode are discussed. About native mode, we propose optimizations for threadlevel and data-level parallelism. We exploit the thread-level parallelism by relaxing inter-thread dependence. The optimized algorithm is proved to be more scalable. Data-level parallelism is exploited by 512-bits single instruction multiple data (SIMD) instructions. The maximum speedup we further gain is up to 3.4 times. About offload mode, we present an offload algorithm. By careful task partition and communication optimizations, it can gain speedup for large graphs which can't run natively on MIC as the limited memory size. We believe that the work is valuable for using MIC to accelerate the BFS. Meanwhile, it's a general evaluation of the MIC for data-intensive applications.

Cooperative and out‐of‐core execution of the irregular wavefront propagation pattern on hybrid machines with Intel® Xeon Phi™

“…The IWPP resembles graph scan algorithms with multiple sources, which have been the target of a number of recent research projects that implemented, for instance, Breadth-First Search (BFS). 22,23 Hong et al 22 presented approaches to minimize the load imbalance that occurs when processing graphs in which the number of edges may vary from vertices. Tao et al 23 Roman, 25 while other works used devices such as Field-Programmable Gate Arrays (FPGAs) and GPUs to implement this operation.…”

“…22,23 Hong et al 22 presented approaches to minimize the load imbalance that occurs when processing graphs in which the number of edges may vary from vertices. Tao et al 23 Roman, 25 while other works used devices such as Field-Programmable Gate Arrays (FPGAs) and GPUs to implement this operation. [26][27][28] A common limitation with these solutions is that they were not built on top of the must efficient sequential algorithm that uses queues.…”

Efficient Irregular Wavefront Propagation Algorithms on Intel(R) Xeon Phi(TM)

“…As such, recent efforts on efficient implementations of Breadth-First Search (BFS) [16] [17] are interesting for the sake of comparison with IWPP execution schemes and optimizations. The work of Hong et al [16], for instance, provides techniques and optimizations to deal with load imbalance from irregular number of edges in vertices from real-world graphs for their GPU-based BFS algorithms.…”

“…Although these techniques have shown to be effective to their work, it would have no impact in IWPP that has a regular and constant number of edges per vertex, represented by the fixed neighborhood. Tao et al [17] is a closer related work that describes approaches to accelerate BFS using the Intel Phi. It develops reading and expansion operations using SIMD instructions, but it still uses atomic (non-vectorized) instructions to perform expansion of vertices.…”

Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster

“…For instance, Hong et al in [6] presented a hybrid method which dynamically decides the best execution method for each BFS-level iteration, shifting between sequential execution, multi-core CPU-only execution, and GPUs. Tao, Yutong and Guang [7] developed two different approaches to improve the performance of BFS algorithm on an Intel Xeon Phi coprocessor.…”