Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

Mariani,; Sima,; Palermo,; Zaccaria,; Silvano,; Bertels,

doi:10.1109/date.2012.6176578

Cited by 23 publications

(16 citation statements)

References 13 publications

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“…The Netchip compiler in Bertozzi et al [2005] explores and generates applicationspecific communication architectures, whereas the authors of Jahr et al [2012] focus on processor architectures at design time and Marianik et al [2012] on runtime reconfigurable processors. Depending on how our architectural approach and presynthesized repository are integrated into other projects, it would be possible to combine one or more of these methods and tools for design space exploration with our contributions.…”

Section: Introduction and Related Workmentioning

confidence: 99%

River

Brugger

Hillenbrand

Balzer

2014

ACM Trans. Reconfigurable Technol. Syst.

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For high-performance embedded hard-real-time systems, ASICs and FPGAs hold advantages over generalpurpose processors and graphics accelerators (GPUs). However, developing signal processing architectures from scratch requires significant resources. Our design methodology is based on sets of configurable building blocks that provide storage, dataflow, computation, and control. Based on our building blocks, we generate hundreds of thousands of our dynamic streaming engine processors that we call DSEs. We store our DSEs in a repository that can be queried for (online) design space exploration. From this repository, DSEs can be downloaded and instantiated within milliseconds on FPGAs. If a loss of flexibility can be tolerated then ASIC implementations are feasible as well. In this article we focus on FPGA implementations. Our DSEs vary in cores, computational lanes, bitwidths, power consumption, and frequency. To the best of our knowledge we are the first to propose online design space exploration based on repositories of precompiled cores that are assembled of common building blocks. For demonstration purposes we map algorithms for image processing and financial mathematics to DSEs and compare the performance to existing highly optimized signal and graphics accelerators. ACM Reference Format:Christian Brugger, Dominic Hillenbrand, and Matthias Balzer. 2014. RIVER: Reconfigurable flow and fabric for real-time signal processing on FPGAs.

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Section: Introduction and Related Workmentioning

confidence: 99%

River

Brugger

Hillenbrand

Balzer

2014

ACM Trans. Reconfigurable Technol. Syst.

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“…Hybrid heuristics (e.g. [20], [28]) provide more flexibility, but they are still limited by relying on off-line profile information. Dynamic prefetching techniques (e.g.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Lifa

Eles

Peng

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Many modern applications exhibit a dynamic and non-stationary behavior, with certain characteristics in one phase of their execution, which change as the application enters new phases, in a manner unpredictable at design-time. In order to meet the demands of such applications, it is important to have adaptive and self-reconfiguring hardware platforms, coupled with intelligent on-line optimization algorithms, that together can adjust to the run-time requirements. Partially dynamically reconfigurable FPGA architectures offer both high performance and flexibility. Despite these potential advantages, the challenges faced by designers trying to set-up a functioning system are still significant, mainly because of the still immature design tools and limited device drivers. We propose a complete framework, based on Xilinx's commercial design suite, that enables an application designer to leverage the advantages of partial dynamic reconfiguration with minimal effort. Our IP-based architecture, together with the comprehensive API, can be employed to accelerate an application by dynamically scheduling hardware prefetches. Moreover, a piecewise linear predictor is used to capture correlations and predict the hardware modules that will generate the highest performance improvement. Our evaluation comprises of extensive simulations, as well as a complete implementation of the SUSAN image processing application on the ML605 board from Xilinx. The measurements show a significant reduction of the expected execution time compared to previous state-of-theart prefetching algorithms, with only a minor energy overhead.Index Terms-FPGA, partial reconfiguration, dynamic configuration prefetching, self-reconfiguring and adaptive platform.

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“…Second, a suitable run-time HW/SW mapping policy should be adopted to map applications' kernels onto the resources, once the actual workload is known, as recommended in previous works [8].…”

Section: Introductionmentioning

confidence: 99%

Run-time optimization of a dynamically reconfigurable embedded system through performance prediction

Mariani

Sima

Palermo

et al. 2013

2013 23rd International Conference on Field Programmable Logic and Applications

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A key tool to increase the exploitation of dynamic reconfigurable platforms is the run-time resource manager. This system module coordinates the usage of both software and reconfigurable hardware resources in the context of a multi-programmed environment, by alleviating the operating system's induced overhead. This paper introduces a two-layers run-time resource manager for dynamic reconfigurable platforms. The upper level is composed of several application-level managers (one for each application) that provide the most suitable mapping based on resource constraints and performance prediction. The lower level is composed of a centralized system-level resource manager that assigns the HW/SW resources to each application. We present a video surveillance case study in which the proposed resource management technique outperforms the performance of the state of the art by 28% on average, introducing a computational time overhead within 2%

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Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures

Cited by 23 publications

References 13 publications

River

River

A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching

Run-time optimization of a dynamically reconfigurable embedded system through performance prediction

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