Using Novel Configuration Techniques for Accelerated FPGA Aging

Gaskin, Tanner; Cook, Hayden; Stirk, Wesley; Lucas, Robert W.; Goeders, Jeffrey; Hutchings, Brad

doi:10.1109/fpl50879.2020.00037

Cited by 9 publications

(4 citation statements)

References 13 publications

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“…The aging speed of FPGAs is normally limited and long-term aging tests cannot be achieved within set time parameters. Hence, it is incredibly important to carry out accelerated tests [30]. In line with the principle regarding the aging mechanisms of BTI, HCI, and the theoretical acceleration model, the aging speed was directly related to the working voltage and temperature of the circuit and their relationships could be expressed as in the following formulae [31]:…”

Section: Accelerated Aging Conditionsmentioning

confidence: 99%

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

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Section: Accelerated Aging Conditionsmentioning

confidence: 99%

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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“…For our High Density Bottom Experiment (originally published in [8], and discussed later in Section 4.3.1), the technique for characterizing the FPGA fabric throughout the experiment is to measure the frequency of distinct ROs one at a time. This technique uses three ROs, as seen in Figure 3.…”

Section: Characterizing With Three Rosmentioning

confidence: 99%

“…The High Density Bottom Experiment (originally published in [8]), uses a bitstream containing 20,798 short circuits, all of which are conigured on the bottom two-thirds of the chip. The layout of this bitstream can be seen in Figure 9a.…”

Section: High Density Bottom Experimentsmentioning

confidence: 99%

“…The initial results of the High Density Bottom Experiment demonstrate that there is a substantial (∼4x) diference in aging between the short circuit region in the bottom two-thirds of the chip and the blank region in the topthird [8]. The Checkerboard Experiment allows us to test if smaller, more complex regions of short circuits see similar localized aging efects.…”

Section: Checkerboard Experimentsmentioning

confidence: 99%

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Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits

Cook

Arscott

George

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

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This work demonstrates a novel method of accelerating FPGA aging by configuring FPGAs to implement thousands of short circuits, resulting in high on-chip currents and temperatures. Patterns of ring oscillators are placed across the chip and are used to characterize the operating frequency of the FPGA fabric. Over the course of several months of running the short circuits, with daily characterization of the FPGA performance, we demonstrate a decrease in FPGA frequency of 8.5%. We demonstrate that this aging is induced in a non-uniform manner. In, two-thirds of the configurable fabric contains short circuits. The maximum slowdown outside of the shorted regions is 2.1%, or about a fourth of the maximum slowdown that is experienced inside the shorted region. In addition, we demonstrate that the slowdown is linear after the first two weeks of the experiment and is unaffected by a recovery period. Additional experiments involving short circuits are also performed to demonstrate the results of our initial experiments are repeatable. These experiments also use a more fine-grained characterization method that provide further insight into the non-uniformed nature of the aging caused by short circuits.

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Aging measurement and empirical modeling of BTI on FPGA using 16 nm FinFETs for static and dynamic stresses

Sobas,

Marc

2023

Microelectronics Reliability

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Using Novel Configuration Techniques for Accelerated FPGA Aging

Cited by 9 publications

References 13 publications

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits

Aging measurement and empirical modeling of BTI on FPGA using 16 nm FinFETs for static and dynamic stresses

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